Analog Storage in the SCA

The output voltage of a cathode preamp/shaper channel is sampled at 20 MHz rate and stored in an SCA channel. There are 6 SCA ASIC's on a cathode FEB. Each SCA ASIC contains 16 channels and each channel has 96 capacitors (cells).

Eight samples for each pulse (see figure below) will be saved. The eight samples include 2 to 3 samples of the baseline voltage for pile-up correction and 5 to 6 samples of the signal pulse for offline reconstruction of the pulse timing and pulse height. The sampling of the preamp-shaper output is a continuous, non-stopping process.

            
The SCA cell addresses for storing the sampled voltage (and addresses for readout of the stored voltages) are generated by the readout control ASIC. The cells to be used in the sampling are kept in a pool of free cells. At any time, 2 blocks (or 16 cells) are taken out of this pool. (since pulses arrive randomely in time, 16 cells are used to ensure the capture of at least 8 samples on a pulse). These cells are put back into the pool a) 400 ns later when no LCT is found (400 ns is LCT decision time); or b) an LCT is found but there is no Level-1 Accept after 3 microsec (Lev-1 latency).

When an (Lev-1)(LCT) coincidence is found after 3 microsec, then the 16 cells are set aside until the stored voltages are digitized and readout. After digitization, the cells are again put back into the pool. The digitization time is

16 channels x 16 samples per channel x 100 ns = 25.6 micro sec

The 100 ns per sample time is driven at moment by the speed of the op-amps in the SCA and not the speed of the ADC. The same bookeeping scheme is applied to all 6 ADC's by a common readout controller on a cathode FEB.