The Readout Controller

The functions of the readout controller is to generate "write" and "read" SCA addresses during data acquisition. The logic of the address generation by the controller is programmed into a XILINX FPGA. The following diagram shows this logic.

To minimize noise generated in the SCA chip, the addresses of the 96 capacitor cells of a given SCA channel are generated following a Gray-code sequence instead of a numerically sequential one. In a Gray-code, the neighboring addresses differ only by 1 bit in binary.

The 96 addresses are organized into 12 blocks of 8 cells each, the higher 4 bits of the word identify the block number and lower 3 bits of the word identify the sub-address of the cell within a block. Both the block addresses and sub-addresses are generated in Gray-code sequences.

The cells to be used in the sampling are kept in a pool of free cells. Since pulses arrive randomely in time, 16 cells (2 blocks) are used to ensure the capture of at least 8 samples on a pulse. The sampling is a continuous process: at any time, 2 blocks (or 16 cells) are taken out of the pool of free cells. These cells are put back into the pool a) 400 ns later when no LCT is found (400 ns is LCT decision time); or b) an LCT is found but there is no Level-1 Accept after 3 microsec (Lev-1 latency).

When an (Lev-1)(LCT) coincidence is found after 3 microsec, the controller generates the addresses of the 16 cells for readout and digitization of the voltages on these cells begins. After digitization, the cells are again put back into the pool.