Digital Monitoring:

Results (1st Chip, 6 Runs): Total Fluence 2.28x10¹² p/cm² Total TID 307 KRads

1. No Latch-up
2. No Shift Errors
3. Supply current increased from 100mA to 220mA starting at about 40 Krads
4. Buckeye gain decreases from 3250 down to 1150 in 300 KRad (see buckeye.pdf ) after 3 Hrs of annealing gain improves back to 1400.
5. Current to Buckeye chip increases from 100mA to 160 mA at 80 Krads then 200mA at 146 Krads.

Results (1^st chip 2 runs 1.05 hrs):Total Fluence 9.9x10¹⁰ p/cm²

1. No Latch-up observed
2. There are about 16 observed changes in the configuration memory due to radiation effects for each true controller interupt. The configuration changes seem to have no effect on the working of the chip. About 70% of Mux controller errors are associated with a change in configuration memory.
3. The SCA control was interrupted 27 times. 26 of the interrupts required full reprogramming of the chip to recover. Four of these interrupts required ~1 second before the chip was properly reprogrammed. Interrupt interval:

Results (1^st chip 4 runs 1.05 hrs):Total Fluence 1.0x10¹¹ p/cm²

1. No Latch-up observed
2. Configuration memory changes due to radiation seem to take place 30 times more often than true Mux controller errors. About 70% of Mux controller errors are associated with a change in configuration memory.
3. The MUX control was interrupted 12 times. All 12 of the interrupts required full reprogramming of the chip to recover. Interrupt interval:

time=1.0x10¹¹/6.0x10¹¹*5.0x10⁷=8.33x10⁶ LHC seconds

8.33x10⁶/12=700,000 s/interrupt

4. Configuration errors (~2000/249111 bits) start happening at end of running (13.3 Krad). These are not cleared by resets.

Results (same chip 2 runs 2.05 hrs):Total Fluence 1.82x10¹¹ p/cm²

1. No Latch-up observed
2. The MUX control was interrupted 22 times. All 22 of the interrupts required full reprogramming of the chip to recover. Interrupt interval:

time=1.82x10¹¹/6.0x10¹¹*5.0x10⁷=1.5x10⁷ LHC seconds

1.5x10⁷/22=700,000 s/interrupt

3. After 10 Krads (additional dose) configuration errors go through the ceiling (~200,000/249111 bits). These are not cleared by resets. They also don't seem to effect the chip functioning. First run stops when MUX stops working (22.2 Krad additional dose). After waiting ~2hrs mux recovers and second run is taken. 

Results (1^st chip 3 runs 1.05 hrs): Total Fluence 2.8x10¹¹ p/cm² Total TID 47.2 Krad

1. No Latch-up observed
2. No configuration errors were observed.
3. The CPLD control was interrupted 106 times. All 106 of the interrupts required full reprogramming of the chip to recover. Interrupt interval:

time=2.8x10¹¹/6.0x10¹¹*5.0x10⁷=2.33x10⁷ LHC seconds

2.33x10⁷/106=200,000 s/interrupt

4. The CPLD died after 55 minutes (47.2 Krad) and replaced on the next morning.

Results (chip 2 runs 1.0 hrs): Total Fluence 3.06x10¹¹ p/cm² Total TID 41.28 Krad

1. No Latch-up observed
2. No configuration errors were observed
3. The CPLD control was interrupted 117 times. All 117 of the interrupts required full reprogramming of the chip to recover. Interrupt interval:

time=3.06x10¹¹/6.0x10¹¹*5.0x10⁷=2.55x10⁷ LHC seconds

2.55x10⁷/117=200,000 s/interrupt

4. The CPLD died after 60 minutes (41.28 Krad) but a broken cable wire was discovered the next morning, and the CPLD works OK, so this may not be due to radiation.

Results (1^st chip 3 runs 4.0 mins): Total TID 62.5 Krad High Dose Rate (228.75 Rad/s)

1. No Latch-up
2. DAC shows problems at 20Krad. Does not recover fully by next morning so it is replaced.

Results (2^nd chip 3 runs 50 mins): Total TID 36.3 Krad Low Dose Rate (23 Rad/s)

1. No Latch-up
2. DAC shows no problems. Out of ~10000 measurements during this run only once was the input output difference greater than 5 mV. In single case it was shifted by 7 mV.

Results (1^st chip 3 runs 35 mins): Total TID 36 Krad

1. No Latch-up
2. No ADC problems were observed in this run. To look for analog problems see the plot of peak pulse heights for 16 channels versus dose in KRads(click on adc.pdf). To look for stuck bits see individual plots of the number of 1's out of 80 samples for each of 12 ADC bits versus dose in Krads(click on adc2.pdf).

Results (1^st chip 1 run 8.0 mins): Total TID 10.0 Krad

Results (1^st chip 2 runs 33 mins): Total Fluence 1.4x10¹¹ p/cm² Total TID 20 Krad

1. No Latch-up
2. 2 shift errors were seen during this period.

Monitoring:

Results (1^st chip 4 runs 108 mins): Total Fluence 4.82x10¹¹ p/cm² Total TID 65 Krad

1. No Latch-up
2. No ADC problems were observed in this run. To look for analog problems see the plot of peak pulse heights for 16 channels versus dose in Krads (click on sca.pdf). Note this plot has two long runs taken two days apart.

 XILINX VIRTEX FPGA (XCV150-pq240-4c)

Results (1^st chip 7 runs ~3 hours): Total Fluence 6.4x10¹¹ p/cm² Total TID 86 Krad

1. Configuration bit flip and Block RAM bit flip rate is proportional to proton beam current, configure bit error is 100bit/70second, Block RAM bit flip 25bit/70second at 500pA. This is equivalent to 4hr/bit at LHC run. The power supply current increase suddenly at 60Krad from 93mA to 300mA and slowly went down to normal over about 5 minutes. At 78 Krad, the current draw is more than 1A (limit of power supply). Check the resistance from power to ground, it is MegaOhms. 

Results (2^st chip 2 runs ~100 mins): Total Fluence 9.8x10¹¹ p/cm² Total TID 131 Krad

1. Similar configuration bit flip and Block RAM bit flip error rate. The power supply current increased to over 250mA at 60Krad and 500mA at 65Krad, and slowly decreased to 250mA after 2~3 minutes. And the current jumped to 930mA at 111Krad and dropped to 400mA after JTAG reprogramming. There are 3000 bits permanent configuration error. At 120Krad, current jumped to 1A (limit of power supply). After cycled the power, the current back to 600mA, but it surpassed the current limit when reprogramming it.
2. For both chips, the configuration bit flip is random as to FRAME, WORD, BIT. And the permanent bit error on 2^nd chip is also random. There are readback problem and JTAG path problem, so the functional error rate is not given.
3. As a comparison, the SPARTAN XCS30XL (MUX FPGA, run 13) had 627 bit flip in 1 hour at 150pA proton beam, which is about the same rate as VIRTEX.