Connectors:
C1: one 160-pin VME connector, get +5V power from VME crate;
C2: one 4-pin connector, +5V power supply if not in VME crate, can be used as FTC +5V power source if plugged in VME crate;
C3: one 14-pin connector, LVDS JTAG signal from JTAG driver;
C4: one 20-pin connector, connects to CCB, and get CMSCLK, L1ACC etc.;
C5: one 26-pin connector, connects to TMB, get TMB data;
C6: one 26-pin connector, connects to CLCT, and get LCT, the active CFEB boards for the LCT, and CLCT data;
C7: one 26-pin connector, connects to ALCT, and get ALCT data;
C8: five 50-pin connectors, each connects to one CFEB, for CFEB slow control and BUCKEYE references;
C9: five 14-pin connectors, skew-clear, each connects to one CFEB, for CFEB ADC data and clock;
CA: two-way optical fiber adaptor, connects to DDU to transmit data to computer;
CB: 10-pin connector, TTL level JTAG, used if LVDS JTAG is not available;

Switches:
S1: one momentary switch, GLOBAL-RESET;
S2: one momentary switch, CALFPGA-RESET;
S3: one momentary switch, TRGFPGA-RESET;
S4: one 8-bit dip switch, CALFPGA related, default: 11110000 (1 means OPEN or OFF),
       SW1: CCB BX reset enable,
       SW2: CAL_MODE,
       SW3: PMODE,
       SW4: ~sel-tx/rx, GLINK mode,
       SW8: FPGA re-program,
       Others: not used;
S5: one 4-bit dip switch, TRGFPGA related, default: 1000,
       SW1: chamber enable, that is one track in the chamber, readout the whole chamber,
       SW2: not used,
       SW3: LCT-PASS, generates L1ACC by some delay of LCT,
       SW4: FPGA re-program;
S6: one 4-bit dip switch, GLINK mode, default: 0000,
       SW1: DIV0,
       SW2: DIV1, together with DIV0, select the GLINK speed range,
       SW3: HCLKON,
       SW4: LOOPEN.

Jumpers:
J1: fourteen drain jumpers, default ON;
J2: one 4-pin jumper, JTAG source selection (TTL or LVDS), default: 12 ON, 34 OFF to select LVDS;
J3: one 2-pin jumper, GLINK transmitter clock selection, default: ON to select GLINK receiver clock;
J4: one 6-pin jumper, GLINK related, default: 12 ON, 34 ON, 56 ON;
J5: one 10-pin jumper, first available CFEB # in CFEB chain, one ON, four OFF;
J6: one 10-pin jumper, last available CFEB # in CFEB chain, one ON, four OFF;
J7: four 4-pin jumpers, ON/OFF selection for each CFEB, 12 OFF 34 ON if CFEB is there, 12 ON 34 OFF if not.  For example: there are three CFEBs, which are connected as CFEB 2, 3 and 4, the J5 should set as: 34 ON, 12, 56, 78, 9A OFF, J6: 78 ON, 12, 34, 56, 9A OFF, J7.1: 12 ON 34 OFF, J7.2, J7.3 and J7.4: 12 OFF 34 ON.

LEDs:
D1: two LEDs, for FPGA program mode, one for CAL-FPGA, one for TRG-FPGA, normally OFF;
D2: Forty LEDs, FIFO status indicator, they should be reset (OFF) by GLOBAL_RESET;
D3: six LEDs, normally, rxerror OFF, all others ON;
D4: eight LEDs, monitor LEDs.