Connectors:
C1: one 50-pin connector, round overall shielded cables,
connects to DAQMB, 8m long, for slow control signals, etc.
C2: one 14-pin connector, skew-clear, overall and individually
shielded cable, for channel link to DAQMB fifo, 8m long, for ADC data;
C3: one 26-pin connector, skew-clear, overall and individually
shielded cable, for channel link to CLCT, 8m long, for comparator data;
C4: one 4-pin connector, +5V power supply for digital
parts;
C5: one 4-pin connector, +6V power supply for BUCKEYE
amplifier;
C6: six 34-pin connectors, each connects to one layer
of chamber;
C7: two 40-pin connectors, connects to neighbor CFEBs,
for comparator data (track overlap);
C8: one 10-pin connector, TTL JTAG, no use if the board
is connected to DAQMB.
Switches:
S1: one 8-bit DIP switch, for SCAM FPGA, Default
setting 1000,0000 (1 means OPEN or OFF, 0 means ON or CLOSE)
SW2: disable SCA
write clock,
SW6: manually read
out LCT FPGA FIFO,
SW7: manually read
out L1ACC FPGA FIFO,
SW8: re-program
SCAM FPGA,
Other bits: no use;
S2: one momentary switch, SCAM FPGA logic reset;
Jumpers:
J1: five drain wire jumpers, default ON;
J2: seven power on jumpers, default ON;
J3: 3-pin jumper, selects BUCKEYE amplifier power
source. 12 closed to select +5V dirty power, 23 closed to select
regulated +5V clean power, default 23 CLOSED;
J4: 4-pin jumper, selects camparator clock source, 12
closed to select CLCT clock, 34 closed to select CFEB clock, default 12
CLOSED;
J5: 4-pin jumper, selects JTAG source, 12 closed to select
TTL JTAG on CFEB, 34 closed to select LVDS JTAG from DAQMB, default 34
CLOSED;
J6: 4-pin jumpers, sets ADC, SCA reference for upper
set chips, default 12 CLOSED;
J7: 8-pin jumpers, sets ADC, SCA references for middle
set chips, default 34 CLOSED;
J8: 4-pin jumpers, sets ADC, SCA references for lower
set chips, default 34 CLOSED;
J9: six 2-pin jumpers, sets SCA output, default CLOSED;
JA: 10-pin jumper, for SCA write clock delay, default
78 CLOSED;
JB: 10-pin jumper, for SCA write clock delay, default
78 CLOSED;
JC: 10-pin jumper, for SCA write clock width, default
56 CLOSED;
JD: 10-pin jumper, for SCA write clock width, default
12 CLOSED;
JE: 10-pin jumper, for SCA read enable delay, default
12 CLOSED;
LEDs
D1: two LEDs, each for one FPGA programming indicator,
normally OFF;
D2: seven LEDs, SCA write address indicator, after reset,
LED1-6 ON, LED7 OFF;
D3: one LED, RESET and ERROR indicator, normally OFF.