UCLA-OSU Meeting 1/25-1/26/99: Results

---

1. UCLA pipeline on LCT Card
• data only sent to DAQMB for LCT*L1Acc:
• Anode and Cathode LCT processor data (28 bits per LCT?)
• Raw anode data
• Cathode half-strip hits for diagnostic events
• pipeline & register holds ~10 events? (35 at most)
• controller for the pipeline
2. Transmission and Format (bit assignment) of data from LCT cards to DAQMB
• LCT data sent on one 28-bit Channel Link.
• One FIFO per LCT card on DAQMB.
• Reserve bit 16 as a `control word' marker.
• header, tail and error words from CFEBs and DAQMB
• LCT abort of data transmission.
• Why OSU prefers 15-bit or smaller word width:
  • The DDU Board: Short Version
  • The DDU Board: Long Version
• 8-bit data words from LCT cards plus write enable and abort bits
• 7-bit FEB trigger word (5 bits cathode, 7 bits anode) plus `LCT Present' signal
• 1-bit LCT*L1Acc `coincidence found' and `Last word' signals
• 2-bit event type (normal,diagnostic,synch event): may be sent by the MCB (Rice)?
• Raw LCT hit data may need variable # of time samples
• Set via slow control during setup.
• Effects word count, so define as separate event type?
3. Cable & connectors for Channel Links
• UCLA will test SCSI-50HD while OSU will test standard ribbon cable with shield.
4. Crate & backplane
• Standard VME will be used for 1999 testbeam, crate provided by OSU?
• P1 backplane only, no LVDS on backplane.
• Cables used in place of P2 & P3 backplanes for LVDS.
• Custom VME will be used in the final design, crates & backplanes provided by UCLA?
• Use free bits for LVDS: P1(none) P2(~64) P3(~90?)
5. Selection of event type (normal,diagnostic,synch)
• Controlled by MCB (Rice) and distributed on backplane?
• Signal sent by run control to LCT cards via MCB?
• Prescale downloaded at start of run to LCT cards?
• No data for L1Acc with no LCT?
6. Spacing & duration of LCT's on DAQMB
• Synchronize anode & cathode LCT cards; same clock phase?
• BXN from trigger system is +/-1 from true BXN; adjust L1Acc coincidence accordingly.
• Make L1Acc coincidence window an adjustable parameter?
• Strips above threshhold are dead for 400ns
  • Strips must be below threshhold for at least 2 BXNs before `reviving'.
7. FEBrd components for comparator
• LVDS drv/recv, enabled through FEB-neighbor cables
• Take care using pull-ups/downs; use buffers to drive?
• Comparator Modes set via JTAG programmable buffers with defaults set up as buffer passthroughs
• 3 peak time bits and 2 peak mode bits.
• Power supply needed? Filtered 5V OK?
8. JTAG distribution to the LCT cards from DAQMB:
• via cable for the testbeam? Maybe on the backplane...
• via the backplane for the final design.
9. Items to discuss with Rice
• `Event type' distribution for testbeam and long-term (see above)
• Send final results of TMB to DAQMB (~14 bits) for testbeam/long-term?
• Provide calibration pulses to chamber components (FEBs, LCT modules, etc.)
• Followed by LCT and L1Acc signals with appropriate latency.
• Set event type accordingly.
• What will the MCB provide?
• BXN, L1Acc, L1Acc Number, BXN associated with L1Acc
• What will Rice provide for the testbeam?
• 40MHz clock, Reset, BXN, L1Acc, L1Acc Number, BXN associated with L1Acc