under construction, last updated April 20,1998)
The system consists of 3 front-end boards, a mother-board, and a camac-module. A schematic view of the electronics system is show below (click on picture for ps file).
What follows is a brief description of the hardware, and existing software to test these modules.
The CAMAC module consists of a .5 Mword memory with an internal memory address register pointing to the present postion in memory. This memory can be read and written by CAMAC, or externally filled with data from the Mother Board. If the memory address register is greater than a setable memory full register a LAM is generated. A list of CAMAC commands for this module can be found at the following link.
To initialize data taking of each event, the CAMAC internal register has to be set to address zero. When a global trigger is received by the mother board, the digital signal processor (DSP) on the Mother Board immediately begins reading out the FE cards and transfers this data to the memory in the CAMAC module. When this readout is finished the CAMAC module generates a LAM indicating to the DAQ computer that data acquisition should begin. The DAQ computer then reads the CAMAC internal register (which indicates the number of data words to be read in), and then performs a CAMAC block transfer of this data.
Shown in the diagram below is the data format for the CAMAC data. The number of data words read out will be 16X96=1536 words per front end card. Only FE cards with data will be read out. Initially we will read out all three front end cards.
In the diagram above the c's attached to each data bit carry useful information about the sca and global triggers timing. Unpacking the data we will extract which capacitor was used to store the charge. If there are capacitor pedestals we can use this information to correct the data. These bits also store which sampled capacitor corresponds to the beam crossing. Since in the test beam we will take 16 samples while at CMS we will only have 8 samples, we can use this information to reduce the 16 samples to 8.
A preliminary data unpack routine has been written for the CAMAC data. To test this routine, fake data was jammed into the CAMAC module, and then readout and unpacked. The code can be obtained from the following link.
Many CAMAC test routines have been written for our LINUX system using the SCSI Jorway73a controller. The following table gives a list of these programs.
The main purpose of this board is to transfer data from the FE boards to the CAMAC module. This is done using a digital signal processor (DSP) combined with a XLINX FPGA. Both the DSP and the FPGA are loaded via JTAG. One can also send RESETs to both the DSP and FPGA via JTAG.
The XLINX FPGA is also used for loading the preamp/shaper pulser shift registers, as well as firing the pulser. One can also generate local and global triggers for taking pedestal runs. These functions will all be controlled by JTAG. Some examples of JTAG source code are given below.
The FE board digitizes, with a period of 50 nsec, the preamp/shaper pulses from the chamber. This is accomplished by using an analog pipeline incorporating six switched capacitor arrays controlled by a single XLINX FPGA. When digitized the resultant samples are stored temporarily in 2K dual port memories until the mother board grabs the data.
To run the board one needs to load the XLINX FPGA and CPLD FPGA. The XLINX also needs to be reset at the start of a run. These tasks are accomplished via JTAG. Additionally JTAG buffers have been put at the input and output of the dual port memories so these memories can be independently tested. Below is a sample of the high level code we use to read and write these memories (see JTAG section below).
At OSU we run our JTAG from a PC parallel port. A small interface box, refered to as the MOJBLASTER, converts the paralled port signals into the four JTAG signals required to run our system. Several of these will be available at the test beam. If running the software through parallel ports is not possible, we can always resort to running JTAG using a CAMAC module (we do have the drivers).
We have written low level drivers for JTAG on LINUX. We have two separate sets of drivers, one set which writes to /dev/port and the other which uses system functions (outb(), ...) to write to the port directly. The source for these drivers is given below.
In the Cathode system there are a total of 18 separate JTAG devices on the mother board, and three front end boards. The diagram below gives the JTAG connections between these devices. The JTAG enters the mother board at M-SW1 (motherboard switch 1). Using JTAG one can select one of four paths, F1-SW1 (fe board1 switch 1), F1-SW2, F1-SW3, and M-SW2 (motherboard switch 2). One ultimately talks on the FE board to the XLINX SCA controller (LCA), a logic FPGA (CPLD), and JTAG read/write buffers (MEMI/MEMO) or, on the mother board to the digital signal processor (DSP), and the XLINX FPGA (LCA) (Click on image for ps file).
The JTAG devices MEMI and MEMO are used to read and write the 2K memories on the FE boards. The FE board LCA devices allow one to load the SCA controller FPGA, reset this FPGA, perform diagnostics, as well as generating signals needed to read and write the 2K memories. The CLPD device is used to download the logic FPGA.
The JTAG DSP device is used to load the motherboard digital signal processor, or reset this processor. The JTAG LCA device is used to load the motherboard XLINX FPGA, reset this FPGA, as well as control preamp/shaper calibration shift registers, and test/calibration pulsers.
As an example of a high level JTAG subroutine we present the code used to test the 2K memories on the FE boards. These programs are available below.
To start a data run several important steps must be taken in software to initialize the hardware. These are:
During event taking the only necessary steps are:
Programs will be provided to generate constants. The only difference from standard data taking is instead of waiting for GFLT's, one generates data and triggers using JTAG. Data readout will be identical.