For drawing we use exclusively the MOSIS CMOS SCALABLE design rules. The DRC rules have been verified to work by M. Studer so they can be trusted. The technology file is ~ellipro/durkin/magic/lib/magic/sys/durkinp2_cwell.tech27.
For extraction and making CIF files for the linear HP process the prefered technology file is ~ellipro/durkin/magic/lib/magic/sys/durkinp2_hp.tech27. This is the HP technology file obtained from MOSIS so the capacitances and resistances constants are up to date. Although the CIFOUT section of the two technology files is basically the same, there is a slight difference in overglass cutting between the two files. Here we believe the hp technology file is superior.
With large layouts it becomes very difficult to see design rule errors. Fortunately there is a simple proceedure to catch any missed errors.
When MAGIC extracts a design it traces all connections within a design. It knows when lines are disconnected and warns about them. Unfortunately the warning outputs are quite confusing. I know of no simple way around this.
The bottom line from all of this is that a flattened mag file should never show any warnings. If it does there is something wrong.
Even though all lines are now connected they may not be connected the way you want them connected. A program called GEMINI written at the University of Washington will check for all wiring inconsistencies between {name}.sp and {name}.cir files. Unfortunately it runs on {name}.sim files which have already been flattened. The proceedure to run GEMINI is as follows:
Once Gemini runs there is a program which requires signal names but does the same job as Gemini plus more!
Once the connectivity of the design is verified one needs to check FET sizes. The program FIXSD above gives you this information in the file fixsd.err(see previous section). GEMINI will also do this for you.
The program FIXSD provides a list of missing or unmatched capacitors as well as compairing the capacitances of matching capacitors in the {name}.sp and {name}.cir files.
It still needs to be verified that the bonding pads are actually connected to the circuit. A routine called PADPLOT will test the labeling and give you a bonding diagram.
Running PADPLOT along with RESTRACE (see below) guarantees pads are connected properly.
Two programs exist for extracting net resistannces. A routine called RESTRACE, written by S. Durkin) will trace from all pads to all associated FETs outputing resistances. Once again this must be run on a flattened file (mag2flat-see above). To run type: ~durkin/magic/bin/restrace {name}.flat.mag > out.lis
MAGIC internally has a command :EXTRESIS. It only works on flattened magic files. You can flatten files using ~durkin/magic/bin/mag2flat described above. The other drawback to this routine is that it will not trace to pads but only traces from FET to FET. For large .mag files this routine does not seem to work at all.
Both routines can be modified to put resistor information into SPICE files (ask S. Durkin).
On rare occasions MAG to CIF file bloating can merge signal lines or wells. The following proceedure will check for bloat errors. THESE proceedure can wipe out files so BACKUP YOUR mag files before running (better yet have Stan do it).
Form a subdirectory below the directory where your mag files are located. (e.g. magic/cif). Copy the cif file to this directory, read it into magic, and write mag files. MAGIC has an irritating habit of mixing up labels. To clean up the labels one must run: ~durkin/magic/cif2mag/mag2fix {name}.mag . Once this is done run magic, :extract all, and make an .sp file.
Before running gemini on the {name}.sp and {name}.cir files it is necessary to slightly modify these files. The cif file has no nwell and thus sees no difference between VSS/VSS3 (OSU convention). To remove this distinction use EMACS to change VSS3 to VSS in the {name}.cir file. Use EMACS to change unknown! to VSS and VSS3 to VSS in the {name}.sp file. Then run gemini on the resulting files. The nets must completely match.
When a user does not provide a bonding map, MOSIS is very particular about bonding pads. It is a good idea to take a look at the overglass layers (OVG, XP) in the cif file before submitting a chip to mosis wiht their automatic bonding. This is accomplished by running ~durkin/wombat/cif2ps -r {name}.cif out.ps. The output postscript file can be edited to display the OVG and XP layers. You will have to rename the XP layer in the CIF file since cif2ps does not recognise XP layers. Any boxes where there is no wire bond should be removed from the XP layer.
If you provide a bonding diagram the XP layer (used only for wire bonding) should be removed from the CIF file.
Links to source for programs above can be found on this html.