V 51 K 80993278890 or4 Y 0 D 0 0 850 1100 Z 0 i 185 N 111 J 155 480 9 J 115 480 7 J 255 465 2 J 155 465 11 J 255 425 2 J 255 405 2 J 155 405 9 J 155 425 11 J 155 445 11 J 255 445 2 B 4 1 S 4 3 L 165 465 10 0 3 0 1 0 I3 S 8 5 L 165 425 10 0 3 0 1 0 I1 S 7 6 L 165 405 10 0 3 0 1 0 I0 B 7 8 B 8 9 S 9 10 L 165 445 10 0 3 0 1 0 I2 B 9 4 B 2 1 L 120 485 10 0 3 0 1 0 I[3:0] N 115 J 335 435 2 J 425 435 1 S 1 2 L 345 435 10 0 3 0 1 0 O T 745 130 20 0 3 JRG Q 14 0 0 T 700 30 10 0 3 A T 700 50 10 0 3 1 T 30 30 10 0 3 Copyright (c) 1994, Xilinx Inc. T 500 100 10 0 3 VIRTEX Family OR4 Macro T 460 50 10 0 3 30th September 2003 I 102 virtex2p:ASHEETP 1 410 0 0 1 ' T 500 80 10 0 3 4-Input bus OR gate I 185 virtex2p:OR4 1 255 385 0 1 ' C 115 1 8 0 C 111 3 1 0 C 111 10 6 0 C 111 5 7 0 C 111 6 5 0 E