V 51 K 167868331100 ofd64 Y 0 D 0 0 1700 1100 Z 1 i 200 N 108 J 525 425 8 J 525 270 8 J 200 165 7 J 340 165 9 J 340 270 11 J 525 300 8 J 340 300 11 J 340 425 11 J 525 455 8 J 340 455 11 J 525 735 8 J 525 890 8 J 525 920 8 J 340 920 9 J 340 890 11 J 525 765 8 J 340 765 11 J 340 735 11 J 525 610 8 J 340 610 11 J 340 580 11 J 525 580 8 B 8 1 L 350 430 20 0 3 0 1 0 D[35:32] B 5 2 L 350 275 20 0 3 0 1 0 D[39:36] B 3 4 L 205 170 30 0 3 0 1 0 D[39:0] B 4 5 B 5 7 B 7 6 L 350 305 20 0 3 0 1 0 D[19:16] B 7 8 B 8 10 B 10 9 L 350 460 20 0 3 0 1 0 D[15:12] B 10 21 B 18 11 L 350 740 20 0 3 0 1 0 D[27:24] B 15 12 L 350 895 20 0 3 0 1 0 D[23:20] B 14 13 L 350 925 20 0 3 0 1 0 D[3:0] B 15 14 B 17 15 B 17 16 L 350 770 20 0 3 0 1 0 D[7:4] B 18 17 B 20 18 B 20 19 L 350 615 20 0 3 0 1 0 D[11:8] B 21 20 B 21 22 L 350 585 20 0 3 0 1 0 D[31:28] N 143 J 525 860 2 J 485 860 2 S 2 1 N 89 J 435 140 3 J 205 140 1 J 525 220 2 J 525 530 2 J 525 840 2 J 435 840 3 J 525 685 2 J 435 685 5 J 435 530 5 J 525 375 2 J 435 375 5 J 435 220 5 S 2 1 L 220 140 14 0 3 0 1 0 C S 1 12 S 12 11 S 11 10 S 11 9 S 9 8 S 8 7 S 8 6 S 6 5 S 9 4 S 12 3 N 153 J 525 345 2 J 505 345 5 J 525 190 2 J 505 190 5 J 525 500 2 J 505 500 5 J 525 655 2 J 505 655 5 J 505 810 3 J 525 810 2 J 505 115 3 J 205 115 1 S 4 3 S 6 5 S 8 7 S 9 10 S 8 9 S 12 11 L 220 115 14 0 3 0 1 0 CLR S 6 8 S 2 6 S 11 4 S 4 2 S 2 1 N 66 J 645 455 8 J 735 455 11 J 645 610 8 J 735 610 11 J 645 920 8 J 855 935 7 J 735 935 9 J 735 920 11 J 645 765 8 J 735 765 11 J 735 300 9 J 645 300 8 B 3 4 L 645 615 20 0 3 0 1 0 Q[11:8] B 2 4 B 5 8 L 645 925 20 0 3 0 1 0 Q[3:0] B 7 6 L 755 940 30 0 3 0 1 0 Q[19:0] B 8 7 B 10 8 B 9 10 L 645 770 20 0 3 0 1 0 Q[7:4] B 4 10 B 12 11 L 645 305 20 0 3 0 1 0 Q[19:16] B 11 2 B 1 2 L 645 460 20 0 3 0 1 0 Q[15:12] N 146 J 485 705 2 J 525 705 2 S 1 2 N 148 J 525 550 2 J 485 550 2 S 2 1 N 151 J 485 395 2 J 525 395 2 S 1 2 N 131 J 485 240 2 J 525 240 2 S 1 2 I 152 virtex2p:VCC 1 485 375 1 1 ' C 151 1 2 0 I 142 virtex2p:VCC 1 485 840 1 1 ' C 143 2 2 0 I 128 virtex2p:VCC 1 485 220 1 1 ' C 131 1 2 0 I 145 virtex2p:VCC 1 485 685 1 1 ' C 146 1 2 0 I 149 virtex2p:VCC 1 485 530 1 1 ' C 148 2 2 0 I 184 OFDDR4CE 1 525 180 0 1 ' C 89 3 10 0 C 66 12 4 0 C 108 2 8 0 C 108 6 1 0 C 153 3 6 0 C 131 2 2 0 I 185 OFDDR4CE 1 525 335 0 1 ' C 89 10 10 0 C 66 1 4 0 C 108 1 8 0 C 108 9 1 0 C 153 1 6 0 C 151 2 2 0 I 186 OFDDR4CE 1 525 490 0 1 ' C 148 1 2 0 C 153 5 6 0 C 108 19 1 0 C 108 22 8 0 C 66 3 4 0 C 89 4 10 0 I 187 OFDDR4CE 1 525 645 0 1 ' C 89 7 10 0 C 66 9 4 0 C 108 11 8 0 C 108 16 1 0 C 153 7 6 0 C 146 2 2 0 I 69 virtex:BSHEETL 1 1260 0 0 1 ' T 1585 0 25 0 3 Page 23 Q 11 0 0 T 35 1040 30 0 3 the D byte goes out last (on C rising edge) Q 14 0 0 T 1570 50 10 0 9 1 T 1560 30 10 0 3 A T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 30 40 10 0 3 drawn by KS T 1560 75 30 0 3 JRG Q 14 0 0 T 1445 50 10 0 9 16th December 2003 T 1440 100 10 0 9 VIRTEX Family OFDDR40 Macro T 1495 80 10 0 9 40-Bit Output DDR Flip-Flop w/Asynchronous Clear T 35 1015 30 0 3 the F byte goes out first (on C falling edge) Q 14 0 0 I 188 OFDDR4CE 1 525 800 0 1 ' C 143 1 2 0 C 153 10 6 0 C 108 13 1 0 C 108 12 8 0 C 66 5 4 0 C 89 5 10 0 E