V 51 K 147794880500 comp4 Y 0 D 0 0 1100 850 Z 10 i 73 I 32 virtex2p:AND4 1 620 430 0 1 ' C 48 2 6 0 C 31 1 1 0 C 45 2 3 0 C 30 2 4 0 C 46 2 5 0 I 34 virtex2p:XNOR2 1 360 360 0 1 ' C 46 1 1 0 C 36 9 2 0 C 35 10 3 0 I 33 virtex2p:XNOR2 1 360 420 0 1 ' C 35 9 3 0 C 36 7 2 0 C 30 1 1 0 I 42 virtex2p:XNOR2 1 360 480 0 1 ' C 35 8 3 0 C 36 10 2 0 C 45 1 1 0 I 43 virtex2p:XNOR2 1 360 540 0 1 ' C 31 3 1 0 C 36 6 2 0 C 35 7 3 0 I 49 virtex2p:ASHEETL 1 660 0 0 1 ' N 48 J 830 480 1 J 700 480 2 S 2 1 L 800 480 10 0 3 0 1 0 EQ N 31 J 620 510 2 J 590 510 3 J 440 570 2 J 590 570 3 S 2 4 S 2 1 S 3 4 L 510 570 10 0 3 0 1 0 AB0 N 45 J 440 510 2 J 620 490 2 J 570 490 3 J 570 510 3 S 3 4 S 3 2 S 1 4 L 510 510 10 0 3 0 1 0 AB1 N 30 J 440 450 2 J 620 470 2 J 570 470 3 J 570 450 3 S 4 3 S 3 2 S 1 4 L 510 450 10 0 3 0 1 0 AB2 N 46 J 440 390 2 J 620 450 2 J 590 450 3 J 590 390 3 S 4 3 S 3 2 S 1 4 L 510 390 10 0 3 0 1 0 AB3 T 30 40 10 0 3 drawn by KS T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 750 100 10 0 3 VIRTEX Family COMP4 Macro T 750 80 10 0 3 4-Bit Identity Comparator T 710 50 10 0 3 12th January 1993 T 950 50 10 0 3 1 T 950 30 10 0 3 A N 36 J 240 595 9 J 200 595 7 J 240 520 11 J 240 460 11 J 240 580 11 J 360 580 2 J 360 460 2 J 240 400 9 J 360 400 2 J 360 520 2 B 4 3 B 3 5 S 3 10 L 250 520 10 0 3 0 1 0 A1 S 8 9 L 250 400 10 0 3 0 1 0 A3 S 4 7 L 250 460 10 0 3 0 1 0 A2 S 5 6 L 250 580 10 0 3 0 1 0 A0 B 8 4 B 5 1 B 2 1 L 205 600 10 0 3 0 1 0 A[3:0] N 35 J 320 345 9 J 320 560 9 J 320 500 11 J 320 440 11 J 320 380 11 J 200 345 7 J 360 560 2 J 360 500 2 J 360 440 2 J 360 380 2 B 4 3 S 2 7 L 330 560 10 0 3 0 1 0 B0 S 3 8 L 330 500 10 0 3 0 1 0 B1 S 4 9 L 330 440 10 0 3 0 1 0 B2 S 5 10 L 330 380 10 0 3 0 1 0 B3 B 1 5 B 5 4 B 3 2 B 6 1 L 205 350 10 0 3 0 1 0 B[3:0] E