V 51 K 324283016400 buf5e Y 0 D 0 0 1100 850 Z 10 i 63 N 30 J 770 370 11 J 770 410 11 J 770 450 11 J 770 490 11 J 770 360 9 J 820 360 7 J 570 530 2 J 770 530 9 J 570 490 2 J 570 450 2 J 570 410 2 J 570 370 2 B 5 1 B 1 2 B 2 3 B 3 4 S 7 8 L 730 530 10 0 3 0 1 0 O0 S 9 4 L 730 490 10 0 3 0 1 0 O1 S 10 3 L 730 450 10 0 3 0 1 0 O2 S 11 2 L 730 410 10 0 3 0 1 0 O3 S 12 1 L 730 370 10 0 3 0 1 0 O4 B 4 8 B 5 6 L 785 365 10 0 3 0 1 0 O[4:0] N 45 J 470 390 3 J 500 390 2 J 500 430 2 J 470 430 5 J 470 470 5 J 500 510 2 J 500 470 2 J 470 510 5 J 300 550 1 J 470 550 5 J 500 550 2 S 1 4 S 1 2 S 8 6 S 5 7 S 5 8 S 8 10 S 9 10 L 310 550 10 0 3 0 1 0 E S 10 11 S 4 5 S 4 3 N 33 J 300 355 9 J 245 355 7 J 300 370 11 J 300 410 11 J 300 450 11 J 300 490 11 J 500 530 2 J 300 530 9 J 500 490 2 J 500 450 2 J 500 410 2 J 500 370 2 B 1 3 B 4 5 B 5 6 S 8 7 L 310 530 10 0 3 0 1 0 I0 S 6 9 L 310 490 10 0 3 0 1 0 I1 S 5 10 L 310 450 10 0 3 0 1 0 I2 S 4 11 L 310 410 10 0 3 0 1 0 I3 S 3 12 L 310 370 10 0 3 0 1 0 I4 B 6 8 B 3 4 B 2 1 L 250 360 10 0 3 0 1 0 I[4:0] I 63 virtex:BUFE 1 500 360 0 1 ' A 555 355 10 0 3 1 RLOC=X0Y8 C 30 12 8 0 C 33 12 6 0 C 45 2 7 0 I 62 virtex:BUFE 1 500 400 0 1 ' A 555 395 10 0 3 1 RLOC=X0Y6 C 45 3 7 0 C 33 11 6 0 C 30 11 8 0 I 61 virtex:BUFE 1 500 440 0 1 ' A 555 435 10 0 3 1 RLOC=X0Y4 C 30 10 8 0 C 33 10 6 0 C 45 7 7 0 I 60 virtex:BUFE 1 500 480 0 1 ' A 555 475 10 0 3 1 RLOC=X0Y2 C 45 6 7 0 C 33 9 6 0 C 30 9 8 0 T 995 70 30 0 3 JRG Q 14 0 0 T 950 30 10 0 3 A T 960 50 10 0 9 1 T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 30 40 10 0 3 drawn by KS T 950 80 10 0 9 5-Bit 3-State Buffer T 1000 100 10 0 9 VIRTEX Family BUFE5 Macro T 890 50 10 0 9 25th September 2003 I 40 virtex:BUFE 1 500 520 0 1 ' A 555 515 10 0 3 1 RLOC=X0Y0 C 30 7 8 0 C 33 7 6 0 C 45 11 7 0 I 49 virtex:ASHEETL 1 660 0 0 1 ' T 750 70 10 0 3 w/ an Active High Enable, RPM E