V 51 K 367470657800 or18 Y 0 D 0 0 850 1100 Z 0 i 83 N 83 J 295 820 2 J 415 820 1 S 1 2 L 325 820 20 0 3 0 1 0 O N 47 J 215 850 2 J 170 850 9 J 215 830 2 J 170 830 11 J 215 810 2 J 170 810 11 J 215 790 2 J 170 790 11 J 105 770 7 J 170 770 9 B 9 10 L 105 780 20 0 3 0 1 0 I[3:0] B 10 8 S 8 7 L 190 790 10 0 3 0 1 0 I3 B 8 6 S 6 5 L 190 810 10 0 3 0 1 0 I2 B 6 4 S 4 3 L 190 830 10 0 3 0 1 0 I1 B 4 2 S 2 1 L 190 850 10 0 3 0 1 0 I0 I 48 virtex:ASHEETP 1 410 0 0 1 ' T 802 126 25 0 9 Page 22 Q 11 0 0 T 705 75 30 0 3 JRG Q 14 0 0 T 700 30 10 0 3 A T 710 50 10 0 9 1 T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 30 40 10 0 3 drawn by KS T 595 100 10 0 9 VIRTEX Family AND4 Macro T 585 80 10 0 9 4-Bit AND Gate w/bus input T 630 50 10 0 9 3rd October 2003 I 74 virtex:AND4 1 215 770 0 1 ' C 47 7 5 0 C 47 5 4 0 C 47 3 3 0 C 47 1 1 0 C 83 1 6 0 E