V 51 K 367470657800 or18 Y 0 D 0 0 850 1100 Z 0 i 98 N 98 J 310 710 1 J 355 710 2 S 1 2 L 330 710 10 0 3 0 1 0 I8 N 97 J 310 690 1 J 355 690 2 S 1 2 L 330 690 10 0 3 0 1 0 I9 N 93 J 355 730 2 J 295 730 2 S 2 1 L 310 730 14 0 3 0 1 0 INT1 N 90 J 555 720 1 J 435 720 2 S 2 1 L 465 720 20 0 3 0 1 0 O T 705 75 30 0 3 JRG Q 14 0 0 T 700 30 10 0 3 A T 710 50 10 0 9 1 T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 30 40 10 0 3 drawn by KS T 630 50 10 0 9 3rd October 2003 I 74 virtex:AND4 1 215 770 0 1 ' C 47 19 5 0 C 47 17 4 0 C 47 15 3 0 C 47 13 1 0 C 83 2 6 0 I 85 virtex:AND4 1 215 680 0 1 ' C 93 2 6 0 C 47 9 1 0 C 47 11 3 0 C 47 7 4 0 C 47 5 5 0 N 83 J 345 750 3 J 295 820 2 J 345 820 3 J 355 750 2 S 1 3 S 1 4 S 2 3 L 310 820 14 0 3 0 1 0 INT0 I 92 virtex:AND4 1 355 670 0 1 ' C 97 2 5 0 C 98 2 4 0 C 93 1 3 0 C 83 4 1 0 C 90 2 6 0 N 47 J 215 655 1 J 170 655 11 J 215 635 1 J 170 635 11 J 215 700 2 J 170 700 11 J 215 720 2 J 170 720 11 J 215 760 2 J 170 760 11 J 215 740 2 J 170 740 11 J 215 850 2 J 170 850 9 J 215 830 2 J 170 830 11 J 215 810 2 J 170 810 11 J 215 790 2 J 170 790 11 J 90 395 7 J 170 395 9 S 6 5 L 190 700 10 0 3 0 1 0 I7 S 8 7 L 190 720 10 0 3 0 1 0 I6 S 14 13 L 190 850 10 0 3 0 1 0 I0 S 16 15 L 190 830 10 0 3 0 1 0 I1 S 18 17 L 190 810 10 0 3 0 1 0 I2 S 20 19 L 190 790 10 0 3 0 1 0 I3 B 21 22 L 90 405 20 0 3 0 1 0 I[9:0] B 10 20 B 20 18 B 18 16 B 16 14 B 6 8 B 8 12 S 12 11 L 190 740 10 0 3 0 1 0 I5 B 12 10 S 10 9 L 190 760 10 0 3 0 1 0 I4 B 2 6 B 22 4 B 4 2 S 4 3 L 190 635 10 0 3 0 1 0 I9 S 2 1 L 190 655 10 0 3 0 1 0 I8 I 48 virtex:ASHEETP 1 410 0 0 1 ' T 595 100 10 0 9 VIRTEX Family AND10 Macro T 585 80 10 0 9 10-Bit AND Gate w/bus input E