V 51 K 171914497300 sr18ce Y 0 D 0 0 1700 1100 Z 1 i 95 N 73 J 170 50 1 J 440 50 3 J 510 960 2 J 440 960 3 J 510 840 2 J 440 840 5 J 510 720 2 J 440 720 5 J 440 600 5 J 510 600 2 S 9 10 S 9 8 S 8 7 S 8 6 S 6 5 S 6 4 S 4 3 S 2 9 S 1 2 L 190 50 10 0 9 0 1 0 C N 71 J 170 1000 1 J 510 1000 2 S 1 2 L 210 1000 10 0 9 0 1 0 SLI I 54 virtex:FDCE 1 510 800 0 1 ' L 610 810 10 0 9 0 1 0 Q1 C 73 5 3 0 C 70 4 2 0 C 94 3 6 0 C 95 3 1 0 C 95 25 4 0 I 55 virtex:FDCE 1 510 680 0 1 ' L 610 690 10 0 9 0 1 0 Q2 C 73 7 3 0 C 70 6 2 0 C 94 2 6 0 C 95 20 1 0 C 95 14 4 0 I 56 virtex:FDCE 1 510 560 0 1 ' L 610 570 10 0 9 0 1 0 Q3 C 73 10 3 0 C 70 9 2 0 C 94 1 6 0 C 95 10 1 0 C 95 16 4 0 I 53 virtex:FDCE 1 510 920 0 1 ' L 610 930 10 0 9 0 1 0 Q0 C 73 3 3 0 C 70 2 2 0 C 94 4 6 0 C 71 2 1 0 C 95 7 4 0 T 30 1050 10 0 3 Copyright (c) 1993, Xilinx Inc. T 1550 30 10 0 3 A T 1560 50 10 0 9 1 T 30 1060 10 0 3 drawn by KS T 1485 70 10 0 9 Shift Register w/ Enable and Async Clr T 1620 75 30 0 3 JRG Q 14 0 0 N 94 J 510 570 2 J 510 690 2 J 510 810 2 J 510 930 2 J 460 930 3 J 460 810 5 J 460 690 5 J 460 570 5 J 460 30 3 J 170 30 1 S 8 1 S 7 2 S 6 3 S 5 4 S 6 5 S 7 6 S 8 7 S 9 8 S 10 9 L 210 30 10 0 9 0 1 0 CLR N 70 J 170 980 1 J 510 980 2 J 420 980 5 J 510 860 2 J 420 860 5 J 510 740 2 J 420 740 5 J 420 620 3 J 510 620 2 S 1 3 L 200 980 10 0 9 0 1 0 CE S 3 2 S 5 3 S 5 4 S 7 5 S 7 6 S 8 7 S 8 9 N 95 J 835 1015 7 J 780 1015 9 J 510 880 2 J 480 880 3 J 480 920 3 J 660 920 3 J 630 1000 2 J 660 1000 5 J 780 1000 11 J 510 640 2 J 480 640 3 J 480 680 3 J 660 680 3 J 630 760 2 J 660 760 5 J 630 640 2 J 780 640 9 J 780 760 11 J 780 880 11 J 510 760 2 J 480 760 3 J 480 800 3 J 660 800 3 J 660 880 5 J 630 880 2 B 9 2 S 4 3 S 4 5 S 5 6 S 6 8 S 7 8 S 8 9 L 760 1000 10 0 9 0 1 0 Q0 B 19 9 S 11 10 S 11 12 S 12 13 S 13 15 S 14 15 S 15 18 L 760 760 10 0 9 0 1 0 Q2 S 16 17 L 760 640 10 0 9 0 1 0 Q3 B 17 18 B 18 19 S 24 19 L 760 880 10 0 9 0 1 0 Q1 S 21 20 S 21 22 S 22 23 S 23 24 S 25 24 B 2 1 L 830 1020 10 0 9 0 1 0 Q[0:3] I 72 virtex:BSHEETL 1 1260 0 0 1 ' T 1470 100 10 0 9 VIRTEX Family SR4CE Macro T 1570 80 10 0 9 4-bit Serial-In Parallel-Out, REVERSED ORDER on OUTPUT BUS! T 1480 50 10 0 9 3rd October 2003 E