V 50 K 237724933600 opad64 Y 0 D 0 0 850 1100 Z 0 i 100 I 91 virtex:OPAD16 1 440 700 0 1 ' C 95 2 5 0 I 89 virtex:OPAD16 1 440 745 0 1 ' C 95 7 5 0 I 87 virtex:OPAD16 1 440 790 0 1 ' C 95 5 5 0 T 700 30 10 0 3 A T 710 50 10 0 9 1 T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 30 40 10 0 3 drawn by KS T 695 75 30 0 3 JRG Q 14 0 0 T 600 100 10 0 9 VIRTEX Family OPAD64 Macro I 92 virtex:OPAD16 1 440 655 0 1 ' C 95 10 5 0 I 96 virtex:OPAD 1 440 620 0 1 ' C 95 1 1 0 I 97 virtex:OPAD 1 440 585 0 1 ' C 95 14 1 0 N 95 J 440 630 2 J 440 710 8 J 190 840 7 J 300 840 9 J 440 800 8 J 300 800 11 J 440 755 8 J 300 755 11 J 300 710 11 J 440 665 8 J 300 665 11 J 300 630 11 J 300 595 9 J 440 595 2 S 12 1 L 330 630 20 0 3 0 1 0 O64 B 9 2 L 325 715 20 0 3 0 1 0 O[31:16] B 3 4 L 200 845 30 0 3 0 1 0 O[65:0] B 6 4 B 6 5 L 325 805 20 0 3 0 1 0 O[63:48] B 8 6 B 8 7 L 325 760 20 0 3 0 1 0 O[47:32] B 9 8 B 11 9 B 11 10 L 325 670 20 0 3 0 1 0 O[15:0] B 12 11 B 13 12 S 13 14 L 330 595 20 0 3 0 1 0 O65 T 555 80 10 0 9 66-bit Output Pad I 48 virtex:ASHEETP 1 410 0 0 1 ' T 600 50 10 0 9 24th May 2002 E