V 51 K 167868331100 ofd64 Y 0 D 0 0 1700 1100 Z 1 i 123 I 123 OFD_33 1 525 180 0 1 ' C 89 1 2 0 C 108 1 15 0 C 66 1 3 0 I 122 OFD_33 1 525 300 0 1 ' C 66 4 3 0 C 108 3 15 0 C 89 4 2 0 I 121 OFD_33 1 525 420 0 1 ' C 89 6 2 0 C 108 6 15 0 C 66 6 3 0 I 120 OFD16_33 1 525 660 0 1 ' C 89 10 2 0 C 108 10 15 0 C 66 10 3 0 N 66 J 645 260 2 J 825 260 9 J 825 380 11 J 645 380 2 J 825 500 11 J 645 500 2 J 825 620 11 J 645 860 8 J 825 860 11 J 645 740 8 J 825 740 11 J 645 620 2 J 825 935 9 J 965 935 7 B 2 3 S 1 2 L 690 260 20 0 3 0 1 0 Q35 S 4 3 L 690 380 20 0 3 0 1 0 Q34 B 11 9 B 13 14 L 835 940 30 0 3 0 1 0 Q[35:0] S 12 7 L 690 620 20 0 3 0 1 0 Q32 B 7 11 B 10 11 L 685 745 20 0 3 0 1 0 Q[15:0] B 8 9 L 685 865 20 0 3 0 1 0 Q[31:16] B 9 13 B 5 7 S 6 5 L 690 500 20 0 3 0 1 0 Q33 B 3 5 N 108 J 525 260 2 J 365 260 11 J 525 380 2 J 365 380 11 J 365 500 11 J 525 500 2 J 525 620 2 J 525 860 8 J 365 860 9 J 525 740 8 J 365 740 11 J 365 620 11 J 225 165 7 J 365 165 9 S 2 1 L 400 260 20 0 3 0 1 0 D35 B 14 2 S 4 3 L 400 380 20 0 3 0 1 0 D34 B 2 4 B 4 5 B 5 12 B 12 11 B 11 10 L 395 745 20 0 3 0 1 0 D[15:0] B 11 9 B 9 8 L 395 865 20 0 3 0 1 0 D[31:16] S 12 7 L 400 620 20 0 3 0 1 0 D32 B 13 14 L 230 170 30 0 3 0 1 0 D[35:0] S 5 6 L 400 500 20 0 3 0 1 0 D33 N 89 J 525 220 2 J 495 220 3 J 495 340 5 J 525 340 2 J 495 460 5 J 525 460 2 J 495 580 5 J 525 820 2 J 495 820 3 J 525 700 2 J 525 580 2 J 495 700 5 J 250 700 1 S 2 3 S 3 5 S 3 4 S 7 12 S 7 11 S 12 10 S 12 9 S 9 8 S 5 6 S 5 7 S 13 12 L 260 700 10 0 3 0 1 0 C S 2 1 I 69 virtex:BSHEETL 1 1260 0 0 1 ' T 1570 50 10 0 9 1 T 1560 30 10 0 3 A T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 30 40 10 0 3 drawn by KS T 1560 75 30 0 3 JRG Q 14 0 0 T 1440 100 10 0 9 VIRTEX Family OFD36 Macro T 1430 80 10 0 9 36-Bit Output D Flip-Flop T 1490 50 10 0 9 29th September 2003 I 118 OFD16_33 1 525 780 0 1 ' C 66 8 3 0 C 108 8 15 0 C 89 8 2 0 I 119 OFD_33 1 525 540 0 1 ' C 66 12 3 0 C 108 7 15 0 C 89 11 2 0 E