V 51 K 150012364800 fd13ce Y 0 D 0 0 1700 1100 Z 1 i 60 I 56 virtex2p:FDSE 1 450 580 0 1 ' L 540 590 10 0 3 0 1 0 Q3 C 55 1 14 0 C 51 4 4 0 C 52 1 1 0 C 53 1 2 0 C 54 1 3 0 I 57 virtex2p:FDSE 1 450 700 0 1 ' L 540 710 10 0 3 0 1 0 Q2 C 55 2 14 0 C 51 3 4 0 C 52 2 1 0 C 53 2 2 0 C 54 2 3 0 I 58 virtex2p:FDSE 1 450 820 0 1 ' L 540 830 10 0 3 0 1 0 Q1 C 55 3 14 0 C 51 2 4 0 C 52 3 1 0 C 53 3 2 0 C 54 3 3 0 I 59 virtex2p:FDSE 1 450 940 0 1 ' L 540 950 10 0 3 0 1 0 Q0 C 55 4 14 0 C 51 1 4 0 C 52 4 1 0 C 53 4 2 0 C 54 4 3 0 N 52 J 450 660 2 J 450 780 2 J 450 900 2 J 450 1020 2 J 250 1020 9 J 250 900 11 J 250 780 11 J 250 660 11 J 250 90 9 J 90 90 7 B 10 9 L 90 100 20 0 3 0 1 0 D[3:0] B 9 8 B 8 7 B 7 6 B 6 5 S 5 4 L 260 1020 10 0 3 0 1 0 D0 S 6 3 L 260 900 10 0 3 0 1 0 D1 S 7 2 L 260 780 10 0 3 0 1 0 D2 S 8 1 L 260 660 10 0 3 0 1 0 D3 N 53 J 450 640 2 J 450 760 2 J 450 880 2 J 450 1000 2 J 370 1000 3 J 370 880 5 J 370 760 5 J 370 640 5 J 370 70 3 J 90 70 1 S 10 9 L 100 70 10 0 3 0 1 0 CE S 9 8 S 8 7 S 7 6 S 6 5 S 5 4 S 6 3 S 7 2 S 8 1 N 54 J 450 620 2 J 450 740 2 J 450 860 2 J 450 980 2 J 390 980 3 J 390 860 5 J 390 740 5 J 390 620 5 J 390 50 3 J 90 50 1 S 10 9 L 100 50 10 0 3 0 1 0 C S 9 8 S 8 7 S 7 6 S 6 5 S 5 4 S 6 3 S 7 2 S 8 1 N 51 J 570 1020 2 J 570 900 2 J 570 780 2 J 570 660 2 J 770 660 9 J 770 780 11 J 770 900 11 J 770 1020 11 J 770 1040 9 J 920 1040 7 B 9 10 L 850 1050 20 0 3 0 1 0 Q[3:0] B 8 9 B 7 8 B 6 7 B 5 6 S 4 5 L 730 660 10 0 3 0 1 0 Q3 S 3 6 L 730 780 10 0 3 0 1 0 Q2 S 2 7 L 730 900 10 0 3 0 1 0 Q1 S 1 8 L 730 1020 10 0 3 0 1 0 Q0 N 55 J 450 690 2 J 450 810 2 J 450 930 2 J 450 1050 2 J 410 1050 3 J 410 930 5 J 410 810 5 J 410 690 5 J 410 30 3 J 90 30 1 S 10 9 L 100 30 10 0 3 0 1 0 SET S 9 8 S 8 7 S 7 6 S 6 5 S 8 1 S 7 2 S 6 3 S 5 4 T 1575 75 30 0 3 JRG Q 14 0 0 T 1560 30 10 0 3 A T 1560 50 10 0 3 1 T 30 1060 10 0 3 drawn by KS T 30 1050 10 0 3 Copyright (c) 1993, Xilinx Inc. T 1360 80 10 0 3 4-Bit Data Register w/ I 50 virtex:BSHEETL 1 1260 0 0 1 ' T 1360 100 10 0 3 VIRTEX Family FD4SE Macro T 1360 70 10 0 3 Clock Enable & Synchronous Set T 1320 50 10 0 3 26th September 2003 E