V 51 K 58180587390 fd18 Y 0 D 0 0 1700 1100 Z 1 i 137 N 137 J 480 750 8 J 340 750 7 B 2 1 L 345 755 20 0 3 0 1 0 Q[47:32] N 136 J 480 640 8 J 340 640 7 B 2 1 L 345 645 20 0 3 0 1 0 Q[31:16] N 135 J 480 860 8 J 340 860 7 B 2 1 L 345 865 20 0 3 0 1 0 Q[63:48] I 113 virtex:FD16CE 1 480 560 0 1 ' C 103 1 4 0 C 136 1 1 0 C 56 4 8 0 C 77 7 7 0 C 118 9 3 0 I 110 virtex:FD16CE 1 480 670 0 1 ' C 118 6 3 0 C 77 5 7 0 C 56 6 8 0 C 137 1 1 0 C 103 2 4 0 I 107 virtex:FD16CE 1 480 780 0 1 ' C 103 4 4 0 C 135 1 1 0 C 56 9 8 0 C 77 3 7 0 C 118 2 3 0 I 95 virtex:FD16CE 1 480 890 0 1 ' C 118 3 3 0 C 77 1 7 0 C 56 1 8 0 C 119 2 1 0 C 103 6 4 0 N 56 J 480 900 2 J 470 900 3 J 205 570 1 J 480 570 2 J 470 570 5 J 480 680 2 J 470 680 5 J 470 790 5 J 480 790 2 S 2 1 S 8 2 S 3 5 L 215 570 10 0 3 0 1 0 CLR S 5 4 S 5 7 S 7 6 S 7 8 S 8 9 N 118 J 205 600 1 J 480 820 2 J 480 930 2 J 440 930 3 J 440 820 5 J 480 710 2 J 440 710 5 J 440 600 5 J 480 600 2 S 5 2 S 4 3 S 5 4 S 7 5 S 7 6 S 8 7 S 8 9 S 1 8 L 215 600 10 0 3 0 1 0 C N 77 J 480 950 2 J 455 950 3 J 480 840 2 J 455 840 5 J 480 730 2 J 455 730 5 J 480 620 2 J 455 620 5 J 455 585 3 J 205 585 1 S 2 1 S 4 2 S 4 3 S 6 4 S 6 5 S 8 6 S 8 7 S 9 8 S 10 9 L 215 585 10 0 3 0 1 0 CE N 119 J 325 970 7 J 480 970 8 B 1 2 L 340 975 20 0 3 0 1 0 D[15:0] N 103 J 600 640 8 J 600 750 8 J 685 750 11 J 600 860 8 J 685 860 11 J 600 970 8 J 685 970 11 J 795 990 7 J 685 990 9 J 685 640 9 B 1 10 L 605 645 20 0 3 0 1 0 Q[15:0] B 7 9 B 9 8 L 725 1000 20 0 3 0 1 0 Q[63:0] B 2 3 L 605 755 20 0 3 0 1 0 Q[31:16] B 4 5 L 605 865 20 0 3 0 1 0 Q[47:32] B 6 7 L 605 975 20 0 3 0 1 0 Q[63:48] B 3 5 B 5 7 B 10 3 T 1580 0 25 0 3 Page 22 Q 11 0 0 T 1570 50 10 0 9 1 T 1560 30 10 0 3 A T 1440 100 10 0 9 VIRTEX Family FD16-64CE Macro T 1545 80 10 0 9 16-64-Bit Bus Matching Register with Asynchronus Clear and Chip + Enable T 1490 50 10 0 9 2nd February 2004 I 31 virtex:BSHEETL 1 1260 0 0 1 ' T 1600 125 25 0 3 JRG Q 14 0 0 E