V 51 K 250961067300 obuft18 Y 0 D 0 0 850 1100 Z 0 i 126 I 94 virtex:PULLUP 1 670 900 3 1 ' C 46 1 1 0 I 90 virtex:PULLUP 1 670 980 3 1 ' C 46 12 1 0 I 41 virtex:BUFE 1 370 930 0 1 ' C 49 2 7 0 C 46 11 8 0 C 47 7 6 0 I 42 virtex:BUFE 1 370 890 0 1 ' C 49 6 7 0 C 46 8 8 0 C 47 5 6 0 I 43 virtex:BUFE 1 370 850 0 1 ' C 49 1 7 0 C 46 3 8 0 C 47 3 6 0 I 88 virtex:PULLUP 1 670 1020 3 1 ' C 46 16 1 0 I 92 virtex:PULLUP 1 670 940 3 1 ' C 46 6 1 0 I 40 virtex:BUFE 1 370 970 0 1 ' C 49 3 7 0 C 46 18 8 0 C 47 10 6 0 N 47 J 105 150 7 J 170 150 9 J 370 860 2 J 170 860 11 J 370 900 2 J 170 900 11 J 370 940 2 J 170 940 11 J 170 980 9 J 370 980 2 B 1 2 L 105 160 20 0 3 0 1 0 I[3:0] B 2 4 S 4 3 L 180 860 10 0 3 0 1 0 I3 B 4 6 S 6 5 L 180 900 10 0 3 0 1 0 I2 B 6 8 S 8 7 L 180 940 10 0 3 0 1 0 I1 B 8 9 S 9 10 L 180 980 10 0 3 0 1 0 I0 N 49 J 370 880 2 J 370 960 2 J 370 1000 2 J 340 1000 3 J 340 960 5 J 370 920 2 J 340 920 5 J 340 880 5 J 340 130 3 J 105 130 1 S 8 1 S 5 2 S 4 3 S 5 4 S 7 5 S 7 6 S 8 7 S 9 8 S 10 9 L 115 130 10 0 3 0 1 0 E T 745 65 30 0 3 JRG Q 14 0 0 T 710 50 10 0 9 1 T 700 30 10 0 3 A T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 30 40 10 0 3 drawn by KS T 500 70 10 0 3 w/ Active High Enable and Pullups on outputs T 802 121 25 0 9 Page 21 Q 11 0 0 N 46 J 670 880 2 J 565 880 3 J 440 860 2 J 565 860 5 J 640 860 9 J 670 920 2 J 565 920 3 J 440 900 2 J 565 900 5 J 640 900 11 J 440 940 2 J 670 960 2 J 565 960 3 J 565 940 5 J 640 940 11 J 670 1000 2 J 565 1000 3 J 440 980 2 J 565 980 5 J 640 980 11 J 640 1030 9 J 730 1030 7 S 2 1 S 4 2 S 3 4 S 4 5 L 600 860 10 0 3 0 1 0 O3 B 5 10 S 7 6 S 9 7 S 8 9 S 9 10 L 600 900 10 0 3 0 1 0 O2 B 10 15 S 11 14 S 13 12 S 14 13 S 14 15 L 600 940 10 0 3 0 1 0 O1 B 15 20 S 17 16 S 19 17 S 18 19 S 19 20 L 600 980 10 0 3 0 1 0 O0 B 20 21 B 21 22 L 660 1040 20 0 3 0 1 0 O[3:0] I 48 virtex:ASHEETP 1 410 0 0 1 ' T 610 100 10 0 9 VIRTEX Family BUFE4 Macro T 590 80 10 0 9 4-Bit 3-State Buffer T 640 50 10 0 9 11th December 2003 E