V 51 K 115263305400 buf13 Y 0 D 0 0 850 1100 Z 0 i 102 I 100 virtex:BUF 1 370 385 0 1 ' C 47 1 2 0 C 46 3 1 0 I 98 DDU5ctrl:BUF16 1 370 430 0 1 ' C 46 13 1 0 C 47 13 2 0 I 94 DDU5ctrl:BUF16 1 370 565 0 1 ' C 47 6 2 0 C 46 6 1 0 T 720 75 30 0 3 JRG Q 14 0 0 T 30 40 10 0 3 drawn by KS T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 700 30 10 0 3 A T 710 50 10 0 9 1 T 640 50 10 0 9 15th December 2003 I 92 DDU5ctrl:BUF16 1 370 520 0 1 ' C 46 10 1 0 C 47 9 2 0 I 93 DDU5ctrl:BUF16 1 370 475 0 1 ' C 47 10 2 0 C 46 5 1 0 I 33 virtex:BUF 1 370 405 0 1 ' C 46 1 1 0 C 47 3 2 0 N 47 J 370 395 2 J 170 395 11 J 370 415 2 J 170 415 11 J 170 575 9 J 370 575 8 J 170 530 11 J 170 485 11 J 370 530 8 J 370 485 8 J 80 380 7 J 170 380 9 J 370 440 8 J 170 440 11 B 12 2 B 7 5 B 5 6 L 190 580 20 0 3 0 1 0 I[15:0] B 8 10 L 190 490 20 0 3 0 1 0 I[47:32] B 2 4 B 4 14 B 14 13 L 190 445 20 0 3 0 1 0 I[63:48] B 14 8 B 7 9 L 190 535 20 0 3 0 1 0 I[31:16] B 8 7 S 4 3 L 180 415 10 0 3 0 1 0 I64 S 2 1 L 180 395 10 0 3 0 1 0 I65 B 11 12 L 80 390 20 0 3 0 1 0 I[65:0] N 46 J 440 415 2 J 640 415 11 J 440 395 2 J 640 395 9 J 440 485 8 J 440 575 8 J 755 595 7 J 640 595 9 J 640 575 11 J 440 530 8 J 640 530 11 J 640 485 11 J 440 440 8 J 640 440 11 S 1 2 L 600 415 10 0 3 0 1 0 O64 S 3 4 L 600 395 10 0 3 0 1 0 O65 B 2 14 B 13 14 L 565 445 20 0 3 0 1 0 O[63:48] B 14 12 B 12 11 B 11 9 B 9 8 B 6 9 L 565 580 20 0 3 0 1 0 O[15:0] B 5 12 L 565 490 20 0 3 0 1 0 O[47:32] B 4 2 B 10 11 L 565 535 20 0 3 0 1 0 O[31:16] B 8 7 L 685 605 20 0 3 0 1 0 O[65:0] I 48 virtex:ASHEETP 1 410 0 0 1 ' T 555 80 10 0 9 66-Bit Buffer T 600 100 10 0 9 VIRTEX Family BUF66 Macro E