V 51 K 115263305400 buf13 Y 0 D 0 0 850 1100 Z 0 i 89 I 87 virtex:BUF 1 370 630 0 1 ' C 46 2 1 0 C 47 1 2 0 I 84 virtex:BUF 1 370 675 0 1 ' C 47 3 2 0 C 46 1 1 0 I 42 virtex:BUF 1 370 760 0 1 ' C 46 5 1 0 C 47 9 2 0 I 41 virtex:BUF 1 370 800 0 1 ' C 46 6 1 0 C 47 10 2 0 I 40 virtex:BUF 1 370 840 0 1 ' C 46 7 1 0 C 47 11 2 0 T 30 40 10 0 3 drawn by KS T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 700 30 10 0 3 A T 710 50 10 0 9 1 T 630 50 10 0 9 6th January 2004 T 720 75 30 0 3 JRG Q 14 0 0 I 43 virtex:BUF 1 370 720 0 1 ' C 46 4 1 0 C 47 6 2 0 N 46 J 440 685 2 J 440 640 2 J 640 640 9 J 440 730 2 J 440 770 2 J 440 810 2 J 440 850 2 J 750 890 7 J 640 890 9 J 640 850 11 J 640 810 11 J 640 770 11 J 640 730 11 J 640 685 11 S 1 14 L 600 685 10 0 3 0 1 0 O4 S 2 3 L 600 640 10 0 3 0 1 0 O5 B 3 14 S 4 13 L 600 730 10 0 3 0 1 0 O3 S 5 12 L 600 770 10 0 3 0 1 0 O2 S 6 11 L 600 810 10 0 3 0 1 0 O1 S 7 10 L 600 850 10 0 3 0 1 0 O0 B 9 8 L 680 900 20 0 3 0 1 0 O[5:0] B 10 9 B 11 10 B 12 11 B 13 12 B 14 13 N 47 J 370 640 2 J 170 640 11 J 370 685 2 J 170 685 11 J 170 730 11 J 370 730 2 J 80 390 7 J 170 390 9 J 370 770 2 J 370 810 2 J 370 850 2 J 170 850 9 J 170 810 11 J 170 770 11 B 8 2 B 7 8 L 80 400 20 0 3 0 1 0 I[5:0] S 14 9 L 180 770 10 0 3 0 1 0 I2 S 13 10 L 180 810 10 0 3 0 1 0 I1 S 12 11 L 180 850 10 0 3 0 1 0 I0 B 13 12 B 14 13 B 5 14 S 5 6 L 180 730 10 0 3 0 1 0 I3 S 4 3 L 180 685 10 0 3 0 1 0 I4 S 2 1 L 180 640 10 0 3 0 1 0 I5 B 2 4 B 4 5 T 600 100 10 0 9 VIRTEX Family BUF6 Macro I 48 virtex:ASHEETP 1 410 0 0 1 ' T 555 80 10 0 9 6-Bit Buffer E