V 51 K 367470657800 or18 Y 0 D 0 0 850 1100 Z 0 i 89 N 47 J 215 720 2 J 170 720 11 J 215 740 2 J 170 740 11 J 215 760 2 J 170 760 11 J 215 780 2 J 170 780 11 J 215 860 2 J 170 860 9 J 215 840 2 J 170 840 11 J 215 820 2 J 170 820 11 J 215 800 2 J 170 800 11 J 85 675 7 J 170 675 9 S 2 1 L 190 720 10 0 3 0 1 0 I7 S 4 3 L 190 740 10 0 3 0 1 0 I6 B 17 18 L 85 685 20 0 3 0 1 0 I[7:0] S 10 9 L 190 860 10 0 3 0 1 0 I0 S 16 15 L 190 800 10 0 3 0 1 0 I3 B 8 16 B 16 14 S 14 13 L 190 820 10 0 3 0 1 0 I2 B 14 12 S 12 11 L 190 840 10 0 3 0 1 0 I1 B 12 10 B 6 8 S 8 7 L 190 780 10 0 3 0 1 0 I4 B 4 6 S 6 5 L 190 760 10 0 3 0 1 0 I5 B 2 4 B 18 2 N 83 J 295 790 2 J 415 790 1 S 1 2 L 325 790 20 0 3 0 1 0 O T 705 75 30 0 3 JRG Q 14 0 0 T 700 30 10 0 3 A T 710 50 10 0 9 1 T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 30 40 10 0 3 drawn by KS T 630 50 10 0 9 3rd October 2003 T 802 126 25 0 9 Page xx Q 11 0 0 I 88 virtex2p:AND8 1 215 700 0 1 ' C 83 1 6 0 C 47 9 10 0 C 47 11 9 0 C 47 13 8 0 C 47 15 7 0 C 47 7 1 0 C 47 5 3 0 C 47 3 4 0 C 47 1 5 0 I 48 virtex:ASHEETP 1 410 0 0 1 ' T 615 100 10 0 9 VIRTEX Family AND8_BUS Macro T 585 80 10 0 9 8-Bit AND Gate w/bus input E