V 51 K 250961067300 obuft18 Y 0 D 0 0 850 1100 Z 0 i 143 I 41 virtex:AND2 1 370 920 0 1 ' C 143 5 20 0 C 124 7 18 0 C 47 7 19 0 I 42 virtex:AND2 1 370 880 0 1 ' C 143 3 20 0 C 124 5 18 0 C 47 5 19 0 I 43 virtex:AND2 1 370 840 0 1 ' C 143 1 20 0 C 124 3 18 0 C 47 3 19 0 I 40 virtex:AND2 1 370 960 0 1 ' C 143 7 20 0 C 124 10 18 0 C 47 10 19 0 N 47 J 170 265 7 J 240 265 9 J 370 860 2 J 240 860 11 J 370 900 2 J 240 900 11 J 370 940 2 J 240 940 11 J 240 980 9 J 370 980 2 B 1 2 L 170 275 20 0 3 0 1 0 B[3:0] B 2 4 S 4 3 L 250 860 10 0 3 0 1 0 B3 B 4 6 S 6 5 L 250 900 10 0 3 0 1 0 B2 B 6 8 S 8 7 L 250 940 10 0 3 0 1 0 B1 B 8 9 S 9 10 L 250 980 10 0 3 0 1 0 B0 N 124 J 170 215 7 J 300 215 9 J 370 880 2 J 300 880 11 J 370 920 2 J 300 920 11 J 370 960 2 J 300 960 11 J 300 1000 9 J 370 1000 2 B 1 2 L 170 225 20 0 3 0 1 0 A[3:0] B 2 4 S 4 3 L 310 880 10 0 3 0 1 0 A3 B 4 6 S 6 5 L 310 920 10 0 3 0 1 0 A2 B 6 8 S 8 7 L 310 960 10 0 3 0 1 0 A1 B 8 9 S 9 10 L 310 1000 10 0 3 0 1 0 A0 T 797 126 25 0 9 Page 25 Q 11 0 0 T 745 65 30 0 3 JRG Q 14 0 0 T 710 50 10 0 9 1 T 700 30 10 0 3 A T 30 30 10 0 3 Copyright (c) 1993, Xilinx Inc. T 30 40 10 0 3 drawn by KS N 143 J 450 870 2 J 530 870 9 J 450 910 2 J 530 910 11 J 450 950 2 J 530 950 11 J 450 990 2 J 530 990 11 J 530 1005 9 J 620 1005 7 S 1 2 L 490 870 10 0 3 0 1 0 O3 B 2 4 S 3 4 L 490 910 10 0 3 0 1 0 O2 B 4 6 S 5 6 L 490 950 10 0 3 0 1 0 O1 B 6 8 S 7 8 L 490 990 10 0 3 0 1 0 O0 B 8 9 B 9 10 L 550 1015 20 0 3 0 1 0 O[3:0] I 48 virtex:ASHEETP 1 410 0 0 1 ' T 610 100 10 0 9 VIRTEX Family 4-AND2 Macro T 590 80 10 0 9 4-AND2 Bus Gate T 640 50 10 0 9 1st October 2003 E