Trigger Motherboard (TMB)

The Trigger Motherboard serves as link to the level-1 muon trigger. There is one TMB for each CSC module. The information associated with ALCT and CLCT (generated on the TMB) includes the bunch crossing time, the location and angle of each ALCT and CLCT. When the timing between a CLCT and an ALCT is found to agree within +- 1 bunch crossing, the LCT is a valid one. When more than one valid LCT is found for the chamber, only the best two, as determined by quality factors, are retained and passed on to the MPC along with the ALCT bunch crossing number. (Each MPC spans a 30 degree sector of an endcap station.) The tasks performed by the trigger motherboard are fully pipe-lined and synchronous with the beam-crossing clock.

The latched anode-bit information are also sent by the ALCT board to the TMB board. This information together with the raw cathode and anode LCT trigger data as well as the matched LCT trigger data are all sent to the DMB to be read out in the DAQ data strem for diagnostic purposes.