The information associated with ALCT and CLCT (generated on the TMB) includes the bunch crossing time, the location and angle of each ALCT and CLCT. When the timing between a CLCT and an ALCT is found to agree within +- 1 bunch crossing, the LCT is a valid one. When more than one valid LCT is found for the chamber, only the best two, as determined by quality factors, are retained and passed on to the MPC along with the ALCT bunch crossing number. (Each MPC spans a 30 degree sector of an endcap station.) The tasks performed by the Trigger Motherboard are fully pipe-lined and synchronous with the beam-crossing clock.
The latched anode-bit information are also sent by the ALCT board to the TMB. This information together with the raw cathode and anode LCT trigger data as well as the matched LCT trigger data are all sent to the DMB to be read out in the DAQ data stream for diagnostic purposes.
The readout of the data from each CFEB is initiated by the DAQ Motherboard. The bits that indicate which of the CFEB boards contain SCA-stored analog data are received from the TMB and passed back to the CFEB. Digitization of the SCA samples will begin on the CFEBs if the bit(s) are time-correlated with the Level-1 Accept. The stored samples within a time window of 400 ns for all channels on the CFEB are digitized. The digitized data is sent to the FIFO on the DMB and transfered by optical link to the central DAQ via the DDU and DCC.
The DAQ Motherboards also act as interface to the Run Control and to Slow control. The interfaced functions include downloading of the FPGA firmware and initialization constants, reset of the readout controller on the CFEB, downloading calibration information, downloading commands for turning off bad channels, monitoring of low voltage levels and temperature. JTAG will be used for the slow control. The distribution of low voltage references to the CFEBs is also located on the DAQ Motherboard. Back to EMU Electronics Homepage