Radiation Tests of the Cathode Front-end Board

  CMOS devices were tested for Latchups and Single Event Upsets 
(SEU's) at the UC Davis 63 MeV p Facility. 

  No latchup of any tested ASIC (the Comparator ASIC has not been 
tested yet) or COTS on the FE boards was observed. 

  Analog performances of the Buckeye and SCA ASICs showed negligible  
degradation due to Total Ionizing Dose (TID) effects up to the expected
TID dose (5 Krad) for 10 LHC years at 10**34 luminosity.
 
  SEU rates for all FPGA's were measured and found to be reasonable 
for background flux estimated at 10**34. Measured  SEU Cross Sections 
ranges from (1 - 4)x 10**(-10) cm**2. (The calculated neutron fluence 
at ME11 for 10 LHC year is 6x10**11 /cm**2 - from M. Huhtinen) 

  The only device displaying any real problem was the temperature 
sensor which will be replaced. 
 
  Detailed test procedures and results of ASICs and COTS on the 
CFEB are shown here.  

  The Channel Link Chips could not be properly tested on the board.
They were tested with a special board and results are shown here.

  Comparator ASIC tests were done separately and results are shown here. 

  Bipolar pnp devices (voltage regulators, protection diodes, ...) 
were tested at O.S.U. in a reactor and also in a Co60 source. The
results of these tests were mixed. Protection diodes showed no
radiation damage for ~40 LHC years equivalent running. Voltage 
reference chips also passed the test. Voltage regulators (as 
expected) showed mixed results. We still need to locate a 5V 
power regulator that is rad hard. Test results are summarized 
here. Plots for each tested device can be found here.