The digital signals generated by the comparator network are sent to the TMB as input to the CLCT processor which finds track ``roads" (see figure below) through the 6 cathode layers within in a time interval of 75 ns (CMS TN/95-013). The magnetic field in the endcap causes bending of charged tracks in the direction transverse to the strips (azimuthal direction). High Pt (>10 GeV/c) tracks bend a maximum of 1.8 strips in the 15 cm between the first and sixth layer in the chamber. Low Pt (2.5-10 GeV/c) tracks will bend as much as 7.2 strips in the chamber module.
The CLCT processor cycles through six phases at 40 MHz. The processor normally cycles in the first phase, in which the circuitry finds patterns among the 2-strip wide bits. There are 48 such bits per card, plus an additional 16 bits input from adjacent cards in order to handle all cases of bending tracks. If any "pretrigger" pattern is found in the first phase, then the processor continues through the following phases sequentially. Before the second phase, there is a short delay to allow signals from all layers to arrive, then all signals are latched until the end of the processor cycle. During the second phase, the 2-strip wide bits are interrogated again, to find in this case the "best" possible such pattern (either low-Pt or high-Pt). In the following four phases, additional high-Pt patterns are found among the half-strip bits in time-multiplexed fashion. In case more than one pattern is found, priority encoding circuitry selects the single best pattern per card for output.
The cathode LCT processor consists logically of four pipelined data
sections, coordinated by an LCT controller state machine. A simplified diagram
of the cathode LCT processor is shown above. The input signal
demultiplexor receives comparator network output signals, stretches them to
persist for approximately 75ns to allow for the variation in drift times from
the different chamber layers, and outputs the bits to pattern look-up
circuitry in a particular time-sequenced order. Upon receiving a pretrigger
signal, the controller instructs the signal multiplexor to latch the signals
for a somewhat longer period of time to allow the LCT to be found precisely.
The signal demultiplexor and LCT controller are ideally implemented in an FPGA
for prototyping and converted to an ASIC design for cost savings in final
implementation. The pattern look-up section of the cathode LCT processor simply inputs patterns of hits and outputs pattern ID numbers for all found patterns. The set of patterns allows for missing hits, i.e. 4 out of 6 layers or 5 out of 6 layers, in addition to 6 out of 6 layers. This section must be programmable in order to handle the various types of chambers and to maintain flexibility of triggering. While the pattern look-up could in principle be implemented as AND gates in an FPGA, at present a more cost-effective solution is an array of sixteen 32-kByte static RAM chips.
Since the pattern look-up circuitry can find more than one valid pattern within a given set of input bits, additional circuitry is included to select the most desirable pattern found. This is done by priority encoding: for each track pattern, there is a unique associated 8-bit pattern ID. The pattern ID is assigned according to the desirability of the pattern. For instance, a 6/6 pattern which goes straight through the chamber corresponding to an infinite momentum track will have the highest possible pattern number, 255. At the end of the cathode LCT processor cycle, LCT data is presented at the output and sent by cable to the motherboards. The LCT output includes the best pattern ID number, as well as th represents the full knowledge of the strip pattern found, and can be used as input to a look-up table to find the number of hits and the best estimates of position and angle. The bunch crossing number gives a cross check of system timing. Since the functionality is fixed, the LCT selector can be implemented in ASICs with minimal or no programmability.
Provision is also included in the cathode LCT processor for downloading the pattern lookup tables, and for optional readout of the raw bit patterns from the comparator chips for debugging. The clocking of the comparator and LCT processor chips is done by the motherboard, and is programmable adjustable within the bunch crossing interval.