CSC DAQMB Rev. 4

DAQMB rev 4 is produced for FAST site in 2001.  It collects the CSC data from  CFEBs(Strip charge information) and TMB (Anode timing information and trigger information), and sends the data to computer, via a Giga-bit ethernet card. It is a 9U slave VME board.  It talks with VME controller through the P1 connector (A24D16).  It talks with CCB and TMB through the custom backplane.

DAQMB Connections:
DAQMB connects to five CFEBs (Rev. 7, 8, or 9) via five 50-pin mini-D connector on front through 25-pair one-to-one skewclear cables.  It connects to LVMB via a 26 pin connector with/without the utility board on front.  It connects to VME through a standard VME64X P1 connector, which supply 3.3V, 5V and GA[4:0] in addition to A24D16 VME.  It connects to CCB-2001 and TMB-2001 via custom backplane. It connects to Giga-bit Ethernet card (three cards has been tested, D-link, Netgear and 3com) via the optical fiber on front.

Slow Control of the DAQMB (VME Interface Command):
The VME interface FPGA decodes VME command (A24D16), and transforms to JTAG, Serial Port, etc.
A[23:0] command structure:
A[23:19]: Board select, it matches with the VME64X Geographical Address GA[4:0].  The decoding is common to all the boards in the 9U VME crate.  It will be ignored in VME64 and older backplane.
A[18:0]: Board dependent command.  Common for all DAQMB.
    A[18:12]: Device select.
    A[11:2]: Function select.  The decoding depends on the different device.
    A[1:0]: not used.
Here is the detailed coding for VME command.

Utility Board Signals:
To monitoring the internal signals from the Fine Pitch Ball package FPGA, the Utility Board is used.  It can monitor the VME bus (Data, Address), FIFO status, and other important signals inside FPGAs. Here is the detailed definition of the pin-outs.

Switches:
1. Push button switch (Located at up left): Reset the system logic and CFEB, it is similar to SOFTRESET command from custom backplane.
2. 4-bit SWA switch (Located at up middle): Not used yet.
3. 4-bit SWB switch (Located at lower middle): SWB1: Data path select.  OFF (1) to select optical link, ON (0) to select FIFO --> VME direct path.
                                                                      SWB2-4: Not used yet.
Here is a small picture of the DAQMB.  Here is a bigger picture of the DAQMB.

Power-up Schedules:
On power-up, FIFO MasterReset is required to initialize the FIFOs, then follows the FPGAs re-load schedules.

FPGA Re-load Schedules:
After FPGAs are re-loaded, a Soft Reset is needed (This can be done through CCB, or VME) to initialize the FPGAs, and a Full Setup (proper configuration file is required) is needed to load the delays etc.  Here is a detailed description of the delay setting, and not recommended for changing.
 

Cable_delay[7:0] Setup:
The cable_delay is used to adjust the timing caused by the different skewclear cables delays. The Cable_delay is set by an 8-bit register, saved in the Flash Memory, and loaded on powerup and FPGA re-load. The following is a guideline to set the data bits depending on the cable length. We may need to fine tune the setting (should be no more than +-1) using real data (cosmic ray).
Cable_delay[0]::CFEB_cable_adj: Affect both the LCT and L1A from DMB to CFEBs. For CFEB skewclear cable length <=10m, this bit is 1, for >10m, this bit is 0. This bit is used to preserve the pulse peak position in SCA readout without adjusting the PRE_BLK_END;
Cable_delay[3:1]::TMB_LCT_cable_adj: Affects only the LCTs from DMB to CFEBs. This adjustment should count for both the skewclear cable from CFEB to TMB and DMB to CFEB. Assuming that the Comp_time is set the same across the chambers, and the TMB latency are the same across the chambers, the setting should be: 000 for cable length > 12m, 001 for cable length 12m>=L>10m, and 010 for cable length 10m>=L>=8m, amd 011 for cable length<=7 meters; The ME1/1 has longer cable, but the drift time is shorter, need deal with seperately;
Cable_delay[5:4]::CFEB_DAV_cable_adj: Affects the CFEB Data_available only. These two bits and cable_delay[0] should compensate the round trip of DMB-CFEB skewclear cable. Set it to 00 for cable length >=12m, and 01 for cable length 12m>=L>=8m, and 10 for cable length <=7 meters;
Cable_delay[7:6]::ALCT_DAV_cable_adj: Affects the ALCT_DAV only. This should count for the round trip on the ALCT skew clear cable. Set to 00 for L>12m, 01 for 12m>=L>10m, 10 for 10m>=L>=8m, and 11 for L<=7m
 


Preliminary version finished:  Oct. 15, 2001.

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