# FPGA bit files explanation:
#   D741C:  There are three kinds of bit files, 1. 8 time samples, 2. 16 time 
#           samples, 3. 16 time samples with one SCA block delayed.  The bit 
#           file selection must  be consistent with the anal.ini file.  
#           They are:
#           1.  ver 74, 71, 70 ....
#           2.  ver 73, 72,
#           3.  Ver 77,
#           ver 78, back to 800ns delay, and use state 5 for P10. 
#                  !!! The PREBLKEND should be set to 7 !!!
#           ver 80, same function as v78, modified from different SCH
#           ver 81, added a SCA empty block counter
#   D741E:  There are several versions for it, but the latest is the best
#           ver 48
#   D741U:  Several versions for it, the latest version is prefered, because 
#           it includes all the modifications in it.
#           ver 40: 1 word sent to DDU for each L1ACC without LCT
#           ver 41: 2 words sent to DDU for each L1ACC without LCT
#           ver 42: Modified  header word 1, to record CLCT dav bit11
#           ver 46: Modified CLCT DAV delay to fit the LCT99 board
#           ver 47: Test version, output DAV7, DAV8 to test their timing
#           ver 51: SW1 to enable whole chamber LCT; TMB, CLCT, ALCT timing OK
#   D741V:  There are two kinds of bit files, 1. 8 time samples, 2. 16 time 
#           samples.  The difference between the two kinds is the delay 
#           setting for calibration mode.  There are several pedestal points
#           more in 16 time samples than that in 8 time samples.
#           1.  ver 25, 23, 22, 21
#           2.  ver 24, 20, 19....  
#           ver 26, modified to give another L1ACC to CLCT board in Cal mode
#           ver 27, BUCKEYE shift will also enable CAL_MODE
#   D741G:  XILINX SPARTAN-XL version of D741E (XC4000E).  All the 
#           D741Gs are for 16 time samples.  D741G is used on the 5 CFEBs
#           at FNAL summer 2000, and Spring 2000 UCDavis test.
#   D741H:  XILINX SPARTAN-XL version of D741C (XC4000E).  All the
#           D741Hs are for 16 time samples.  D741H is used on the 5 CFEBs
#           at FNAL summer 2000, and Spring 2000 UCDavis test.
#   D741D:  XC9536 CPLD for CFEB CERN beam test 1999.
#   D741W:  XC9536 CPLD for DAQMB CERN beam test 1999.
#   D741F:  XC9536XL CPLD for CFEB FNAL summer 2000, and Spring 2000 UCDavis
#           Proton radiation test.
#   D741FEB: XILINX Virtex FPGA for pre-production CFEB.  D741FEB*.bit
#           files are for Virtex, while D741FEB*.svf files are for SPROM
#   
#   As a rule, the latest version in each kind is prefered, because it has 
#   the latest modification, such as STATUS words, mistakes.  Some version 
#   may not works, such as ver 76 of D741C, which I did include in the above 
#   listing. The difference between revisions is APR effort, so the higher 
#   resion number may means a better cooking result.
#
# 
########  FPGA configuration Files  ##################
#
FPGA      D741V     MPROM          daqmbc32.svf
FPGA      D741V     VPROM          daqmbv_v15_r1.svf
FPGA      D741V     FAPROM         d741feb_v20_r2.svf
#
#
########  Physical setup ##############################
#
time_samples             16
boards_in_use            1  1  1  1  0
# chips used in each board  board number first
chips_in_use             1  1  1  1  1  1  1
chips_in_use             2  1  1  1  1  1  1
chips_in_use             3  1  1  1  1  1  1
chips_in_use             4  1  1  1  1  1  1
chips_in_use             5  1  1  1  1  1  1
#
########  Configuration settings  ####################
#
crate_id                19
crate_slt               7
ccb_slt                 13
jtag_port                1
calibration_delay        0x3df68   # was 001df before Nov. 30, 2001
feb/daqmb_clock_delay    0x1F   # default is 1F
feb_dav_delay            1  # [4:0] was 0 before Nov. 30, 2001, 1 for new
trigMB_dav_delay         0  # [9:5]     default is 5
push_dav_delay           0x8  # [14:10]   default is 5
l1acc_dav_delay          0x26  # [20:15]   default is 5
#
pul_dac_set              1.0  # initial value (in volts)
inj_dac_set              1.0  # initial value (in volts)
set_comp_thresh          0.05 # initial value (in volts)
comp_mode                2    # 
comp_timing              2    #
pre_block_end            7    # default is 7  # 15 for BlockRAM version
                                              # 7  Dec. 27, 2000.  New CFEB