Test setup: Chips used: Xilinx xcv50-4-pq240 and Data Dealy Device 3D7408-0.25-SOIC
Here is the block diagram of the test setup and this is the FPGA design.  The Delay chip is set to Transparent Parallel Mode, and controled by the registers inside the FPGA.
DLL test Results:

• By quickly changing the delay setting, a changed clock is seen on the delay chip, and DDL input.  With this clock, the DLL works fine.  The output is duty cycle corrected, and LOCKed.  (In this example, the input clock is high/low/high/low...... 14.1ns/11.6ns/12.7ns/11.7ns/14.1ns/11.5ns/12.6ns/11.7ns/......
• Clock interupt test:  By mometarily short the DLL input clock to ground, the DLL keeps LOCKed, and the output gets mometary interupt.  For long time clock interupt (seconds), the DLL sometimes lost LOCK.  A reset is needed to re-LOCK.  Automatically resetting the DLL in case losing LOCK can be easily implemented in the FPGA.
• By changing the delay setting (0 to 30ns), the Delay chip outputs an irregular clock cycle.  In this case, the DLL output a similar irregular clock, and go back to normal clock.  The LOCK does not get interupted.
• For 40MHz clock input, and this xcv50-4, it takes about 45us to get LOCKed.

• The duty cycle changes depending on the clock frequency.  The Delay chip input is from FPGA, 3.3V signal, and the output is 5V signal.  The width is measured at 50% of the pulse (1.6V and 2.5V respectively).  The duty cycle changes little depending on the clock frequency:

Clock frequency	Input_high	Input_low	Output_high	Output_low	Delta(High-low)
20MHz	25.2ns	24.8ns	26.4ns	23.6ns	2.4ns
40MHz	12.2ns	12.8ns	13.5ns	11.5ns	2.6ns
80MHz	6.5ns	6ns	7.9ns	4.6ns	2.8ns

• The delay chip does not work at 160MHz input.  The output is high with a wave on the high level (does not go to 0).  Maybe because of the test setup.
• The falling edge of the delay chip is slower than the rising edge.  The threshold of the delay chip in this test is below 1.5Volt.

Preliminary version finished:  Feb. 25, 2002.

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