CSC DAQMB Rev. 4
Parameter on DAQMB:  There are many parameters because the system is not finalized.
'DAV' Delay setting:  This parameter controls the window position for Data Available from CFEB and TMB.  DAVs are signals from CFEBs and TMB that tells the DAQMB that 'I have data on this L1ACC, be ready to read me out'.
davtime[20:0]  d,dddd,dccc,ccbb,bbba,aaaa
aaaaa: CFEB Data Available delay adjustment (25ns per step);
bbbbb: TMB Data Available delay adjustment (25ns per step);
ccccc: Accept window adjustment (25ns per step);
dddddd: L1ACC latency relative to CLCT (25ns per step).

There are several signals to monitor if the adjustment is OK on DAQMB Controller FPGA firmware version 31 and later through DMB_UTIL board.  To monitor the DAVs, follow these steps:

1. Plug the CFEB input to CFEB3, if you want to adjust CFEB DAV delay.
2. Turn the mode selector on DMB_UTIL board to either 4 or 6.
3. Connect the ossiloscope to the 34-pin connector, see the pin definition below,
4. Set the DAV delay for TMB and/or CFEB and reload the configure file, until the DLYD_TMB_DAV, DLYD_CFEB_DAV and DLYD_L1ACC line up.
Here is the definition of the signals:
    Pin 31:  L1ACC seen by DAQMB
    Pin 27: CFEB DAV latched input
    Pin 25: TMB DAV latched input
    Pin 29: DLYD_ALCT_DAV, Delayed ALCT Data Available
    Pin 23: DLYD_CFEB_DAV, Delayed CFEB Data Available
    Pin 21: DLYD_TMB_DAV, Delayed TMB Data Available
    Pin 19: DLYD_L1ACC, Delayed L1ACC used to match with the delayed DAVs.
'CALIB' Delay setting: This parameter controls the calibration timing.  On calibration, or CFEB test, the DAQMB generate 'fake' LCT and 'fake' L1ACC.  The delay here is set so that the pulse position adjusted, and the time between LCT and L1ACC will simulate the real case, which is not exist right now.
CAL[18:0] ddd,ddcc,cccb,bbbb,aaaa
aaaa: Calibration LCT delay setting (25ns per step);
bbbbb: Calibration L1ACC delay setting (25ns per step);
ccccc: Buckeye PULSE delay setting (6.25ns per step);
ddddd: Buckeye INJECT delay setting (6.25ns per step).
'FEBCLOCK' Clock delay setting: This delay is set to fine tuning the CFEB sampling, so that the sampling will be at the pulse peak..
FC[4:0]: 1ns per step.
Parameters on CFEB:
CMPTIME[2:0]:  Comparator timing setting;

CMPMODE[1:0]: Comparator working mode setting.  For details about CMPTIME and CMPMODE, contact UCLA.

PBLKEND[3:0]: Will adjust the number of time samples before the pulse, used as pedestals.


Preliminary version finished:  Dec. 19, 2001.

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