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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| DDU_CtrlFPGA_sch2009..> | 2011-01-28 10:06 | 1.9M | |
| DDU_InputFPGA_sch200..> | 2011-01-28 10:06 | 1.1M | |
| DDU_VMEfpga_sch.pdf | 2011-01-28 10:06 | 755K | |
| archive/ | 2011-01-28 10:06 | - | |
| DDU_CtrlFPGA_sch2012..> | 2013-10-08 11:52 | 1.6M | |
| DDU_InputFPGA_sch201..> | 2013-10-17 18:14 | 1.2M | |
| OSU-LaptopScreenshot..> | 2014-08-04 16:22 | 2.5M | |
| DDU_CtrlFPGA_sch2014..> | 2014-08-04 17:26 | 1.6M | |
| 0DDUCTRL-sch2015marc..> | 2015-03-16 18:48 | 1.6M | |
| DDU_CtrlFPGA_sch2015..> | 2015-03-16 18:48 | 1.6M | |
| ISE-settings_DDU5ctr..> | 2015-05-21 16:40 | 3.0M | |
| 0DDUCTRL-sch2015may.pdf | 2015-05-22 17:59 | 1.6M | |
| 0DDUCTRL-sch2015june..> | 2015-06-10 17:15 | 1.6M | |
| 0DDUCTRL-sch2015july..> | 2015-07-07 17:03 | 1.6M | |
| 0DDUCTRL-sch2015aug.pdf | 2015-08-10 11:49 | 1.6M | |
| 0DDUCTRL-sch2015sept..> | 2015-09-20 13:40 | 1.6M | |
| 0DDUCTRL-sch2015oct9..> | 2015-10-09 15:29 | 1.6M | |
| 0DDUCTRL-sch2015oct.pdf | 2015-10-12 14:44 | 1.6M | |
| 0DDUCTRL-sch2015.pdf | 2015-11-09 17:07 | 1.6M | |