Old Production Version
Note 1: The current format for the 16-bit DDU input has been designed to easily interface with a 64-bit readout system through S-LINK64 (see Old DDU Output Format). This requires that all data sent to the DDU must have an integer multiple of 4 16-bit words for each event. Furthermore, the highest bit of each 16-bit word from a DMB is reserved as a special flag for `DDU Code' words; since we are constrained by a 16-bit fiber-optic transmission system, only the lowest 15 bits are available for physics data.
Note 2: The 16-bit DDU Code words are always sent in groups of 4 to make a 64-bit DDU word. The lowest 16-bit portion of a 64-bit DDU word is the first word received by the DDU, and is designated as word "a". The second 16-bit portion received by the DDU is word "b", the third is word "c", and the last (and highest) 16-bit part of a 64-bit DDU word is designated as word "d". The DMB-DDU word labels can be distinguished from the HEX codes in this page which use the capital letters A-F, sometimes preceded by the "0x" designator as used in C programming.
15 14 13 12 |
Code |
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DMB Lone Word: L1A received, but no matching LCT on CSC, and no useful data is present. |
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DMB First Header Word: Indicates that more data follows for this event. |
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DMB Second Header Word: Additional DMB event information. |
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SCA Full : An SCA Full condition will result in a missing time sample; the CFEB will send this word in place of data. |
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Status Word: Used to pass internal board/FPGA status signals between devices. |
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Trigger Trailer Word: Last word from the TMB or ALCT for this event (generated by TMB and ALCT). |
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DMB Last Trailer Word: Marks the LAST word from the DMB. |
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DMB First Trailer Word: Indicates End of DMB; the NEXT word is the LAST word from the DMB. |
Header Word | Highest 4 bits | DDU Code | Lowest 12 bits [11:0] |
---|---|---|---|
1a | 1001 | 9 | DMB_L1A[11:0] *recent change, 9/24/04* |
1b | 1001 | 9 | DMB_L1A[23:12] *recent change, 9/24/04* |
1c | 1001 | 9 | TMB_DAV(1) + ALCT_DAV(1) + CFEB_CLCT_SENT(5:1) + CFEB_DAV(5:1) *recent change, 9/24/04* |
1d | 1001 | 9 | DMB_BXN[11:0] |
2a | 1010 | A |
TMB_DAV(1) + CLCT-DAV-Mismatch(1) + ALCT_DAV(1) +
CLCT-DAV-Mismatch(1) + TMB_DAV(1) + CLCT-DAV-Mismatch(1) + ALCT_DAV(1) + CFEB_DAV(5:1) |
2b | 1010 | A | DMB_CRATE(8) + DMB_ID(4) |
2c | 1010 | A | CFEB_MOVLP(5:1) + DMB_BXN[6:0] |
2d | 1010 | A | DMB-CFEB-Sync[3:0] + DMB_L1A[7:0] |
Trailer
Word |
Highest
4 bits |
DDU Code | Lowest 12 bits [11:0] |
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1a | 1111 | F | DMB_BXN[3:0] + DMB_L1A[7:0] |
1b | 1111 | F | CFEB_MOVLP(5:1) + ALCT_HALF(1) + TMB_HALF(1) + CFEB_HALF(5:1) |
1c | 1111 | F | DMB_L1PIPE(8) + ALCT_EMPTY(1) + TMB_EMPTY(1) + ALCT_Start_Timeout(1) + TMB_Start_Timeout(1) |
1d | 1111 | F | CFEB_End_Timeout(5:1) + ALCT_End_Timeout(1) + TMB_End_Timeout(1) + CFEB_Start_Timeout(5:1) |
2a | 1110 | E | ALCT_FULL(1) + TMB_FULL(1) + CFEB_FULL(5:1) + CFEB_EMPTY(5:1) |
2b | 1110 | E | Duplicate Header 2b (DMB Crate & ID) |
2c | 1110 | E | DMB_CRC_LowParity(1) + DMB_CRC[10:0] |
2d | 1110 | E | DMB_CRC_HighParity(1) + DMB_CRC[21:11] |
The First Trailer is a flag for the DDU indicating the DMB is nearly
done.
The Second Trailer is the Last Word from the DMB.
Lone
Word |
Highest
4 bits |
DDU Code | Lowest 12 bits [11:0] |
---|---|---|---|
1a | 1000 | 8 | DMB_L1A[11:0] *recent change, 4/20/05* |
1b | 1000 | 8 | DMB_L1A[23:12] *recent change, 4/20/05* |
1c | 1000 | 8 | 0000.0000.0000 *recent change, 4/20/05* |
1d | 1000 | 8 | DMB_BXN[11:0] |
DMB-DDU Header/Trailer bit definitions (some bits get repeated for bit error mitigation)
CF_WC = {[(16 strips) * (6 layers)] + 1 CRC + 2 CFEB_INFO + 1 End_Marker} * (N_ts)
Each of the 96 SCA data words has the following format:
CFEB Data Bit | Bit Definition |
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15 | Always LOW for data words. HIGH for DDU Code word (e.g. DMB Trailer or Error case 2 above). |
14 | Overlapped sample flag (normally HIGH; set LOW when two separate LCTs share a time sample). |
13 | Serialized CFEB-SCA controller data (trigger time and capacitor block number; see below). |
12 | Out of range flag from CFEB ADC. |
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12-bit Digitized CFEB ADC data. |
The 15-bit CRC word (the 97th word in each time sample) is calculated for the set of 96 SCA data words in a time sample. It is created using a CRC-15 algorithm (description, code, generator) with 1-bit error correct, multiple-bit error detect. Words 98 and 99 contain CFEB Status information:
Word 98: L1PIPE_EMPTY(1) + LCTPIPE_EMPTY(1) + L1PIPE_FULL(1) + LCTPIPE_FULL(1) + LCTPIPE_CNT(4) + NF_SCA(4)L1PIPE and LCTPIPE refer to CFEB-SCA Controller internal pipeline status; NF_SCA is the number of free SCA blocks (12 max). Word 100 is the End of Sample Marker: 0x7FFF.
Word 99: DMB_L1A(6) + L1PIPE_CNT(5) + L1PIPE_WARN(1)
CFEB Data Stream
The ordering of the words in the data stream from a single CFEB is
described by the following nested loops:
do (N_ts time samples){Should an error occur, the CF_WC may deviate from this scheme (case 2 above). Whenever that happens, a DDU Code word will be sent indicating a full condition (see below) that modifies the word count.do (Gray code loop over 16 CSC Strips; S=0,1,3,2,6,7,5,4,12,13,15,14,10,11,9,8){}do (loop over 6 CSC Layers; L=3,1,5,6,4,2){}SCA Data Word}
CRC word
CFEB Info word 98
CFEB Info word 99
Dummy word (0x7FFF)
Serialized CFEB-SCA Controller Data
Bit 13 of each data word carries the serialized 16-bit CFEB-SCA Controller
(SCAC) status word, containing trigger and SCA information. This
data word is serialized (LSB first) with one bit in each of the 16 strips
read out, yielding the 16-bit word. Due to the
innermost-loop
over the 6 CSC layers, each bit of a 16-bit SCAC word is actually sent
6 times in a row (once for each layer). Since there are 16 strips
read out for each time sample, the complete SCAC word can be reconstructed
independently in every time sample. The 16-bit word is defined as
follows (highest-to-lowest bit):
TS_FLAG(1) + SCA_FULL(1) + LCT_PHASE(1) + L1A_PHASE(1) + SCA_BLK(4) + TRIG_TIME(8)
TRIG_TIME indicates which of the eight time samples in the 400ns SCA block (lowest bit is the first sample, highest bit the eighth sample) corresponds to the arrival of the LCT; it should be a fixed phase relative to the peak of the CSC pulse. SCA_BLK is the SCA Capacitor block used for this time sample. L1A_PHASE and LCT_PHASE show the phase of the 50ns CFEB digitization clock at the time the trigger was received (1=clock high, 0=clock low). SCA_FULL indicates lost SCA data due to SCA full condition. The TS_FLAG bit indicates the number of time samples to digitize per event; high=16 time samples, low=8 time samples.
Pattern of Bits
15 14 13 12 |
Pattern of Bits
11 10 9 (error code) |
Code Definition | Lowest 9 bits [8:0] |
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1011 | 001 | CFEB: SCA Capacitors Full | 0 + 4-bit Block Number + 4-bit FIFO1 word count |
1011 | 010 | CFEB: FPGA FIFO full** | 0 + 4-bit FIFO3 word count + 4-bit FIFO1 word count |
** A resynch may be required in this case.
Revision Summary: