CMS CSC(EMU) Data Concentrator
Card (DCC)
DCC is a high speed data concentrator card at 2* GigaByte per second. DCC
collects the CSC data from DDUs data at 10 *
640 MegaByte per second through custom backplane in FED
crate, then sends data to main CMS DAQ at 2* 800 MegaByte per second by SLINK64, and local debug computer at 2* Gigabit per second through fiber gigabitethernet. It also receives TTC control
signals and fan out to the FED crate. DCC
is a 9Ux220mm slave VME board. It talks with VME controller (VME master
in slot 1) through the P1 connector (A24D16).
Production DCC Operation Manual (NEW)
DCC ESR presentation (part of FED ESR)
DCC Photos
DCC presentation with pictures
DCC PCB schematic design (pdf)
DCC data receiver FPGA design (production version .svf)
DCC SLINK interface
FPGA design (Production version .svf)
DCC
Output (SLINK, Gigabit Ethernet) data format
Contact Jianhui for latest FPGA designs and data format
Preliminary version finished: June 28, 2004.
Updated on Mar. 22, 2007.
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