Q. The max data rate for the DS92LV1021 is sometimes quoted as 480 Mbp/s and sometimes as 400 MBit/s; what is the real max data rate?
A. Both numbers are correct: the DS92LV1021 embeds 2 additional bits to the 10 data bits as clock information therefore transmitting 12*40MHz = 480 MBit/s, however, since only 10 of the bits are actually data the "payload" or information rate for each cycle is 10*40MHz = 400 MBit/s. The device is 83% (10/12) efficient.

Q. What's the maximum output frequency of the DS92LV1021?
A. Since the DS92LV1021 has a max. data rate of 480 MBit/s (including the clock information) the maximum frequency output is 1/2 that; 240 MHz. Even though data and clock are serialized there is enough clock information for the DS92LV1210 to clock in each bit so the frequency is 1/2 the data rate (synchronous data) not equal to the data rate as with asynchronous data.

Q. What's a SYNC pattern?
A. A SYNC pattern is a special pattern of ones and zeroes output by the DS92LV1021 to enable the DS92LV1210 to phase lock to the rising edge of the embedded clock. In actuality it is simply 6 ones followed by 6 zeroes. SYNC patterns are automatically output by the 1021, regardless of the data at the DINO-DIN9 inputs, when either the SYNC1 or SYNC2 input is held high.

Q. Is there a powerup sequence for the Serializer?
A. Yes, upon powerup, the Tx PWRDWN pin needs to be toggled from high to low and back to high again to initialize the part. Another way would be to hold the PWRDWN pin low for 1us to make sure VCC pins have stabilized.

Q. What is timing requirement between TCLK and Data inputs?
A. You should not violate setup and hold times at DIN(0-9) and have TCLK jitter <150ps.

Q. Is there a failsafe condition for the Serializer?
A. With floating inputs, all inputs (DINO-9, DEN, PWRDWN, TCLK, TCLK R/F*, SYNC) will be pulled low. This creates a Tri-state condition at the outputs.

Q. What's the purpose of the REFCLK input on the DS92LV1210?
A. The DS92LV1210 REFCLK input serves 2 purposes. First, it is used as a time reference for the clock recovery section. The Deserializer PLL initially locks to this clock and then to the data stream. Second, REFCLK is used to run the internal state machine, which indicates the status (/LOCK, PWRDWN, REN) through the DS92LV1210.

Q. What is the frequency of the REFCLK input?
A. The REFCLK input of the DS92LV1210 should be operated at the same nominal frequency as the TCLK input of the DS92LV1021. For example, if data is being clocked in to the DS92LV1021 at 40 MHz the DS92LV1210 REFCLK should also be 40 MHz. There is no phase requirement between REFCLK and TCLK.

Q. How close does the REFCLK frequency have to be to the TCLK frequency?
A. REFCLK frequency should fall within the following range: 0.97Tclk<REFCLK <1.20Tclk. The spec is asymectrical due to the internal architecture of our device.

Q. Does REFCLK need to be running at all times?
A. We recommend that REFCLK remain running at all times. This is because the REFCLK runs the internal state machine. When the Deserializer shifts lock from REFCLK to embedded clock, then REFCLK can be taken away and the part may still work. However, should the Deserializer lose lock, without the presence of REFCLK the LOCK pin will remain low incorrectly indicating a locked part. Since, REFCLK runs the state machine, without REFCLK the device's lock loss (/LOCK=1) can't be indicated.

Q. How is loss of lock indicated?
A. When the Deserializer loses lock, the lock pin will be asserted high within 4-5 clock cycles. Therefore, the last 5 cycles of data transmitted can be invalid. This should be detected by the protocol.

Q. Once the device loses lock, how can the system resynchronize?
A. The system needs to monitor the lock pin. Once the system detects loss of lock (/LOCK=1), then in order to resynchronize the Deserializer, sync patterns need to be transmitted. Transmission can be achieved through assertion of either the SYNC 1 or SYNC2 pin. The easiest method to detect the lock pin and transmit sync patterns is by feeding back the /Lock output of deserializer to the either of SYNC pins on the serializer

Q. What are typical lock times for the Deserializer?
A. At 40 MHz typical lock time from PWRDWN is 4.8 us and 4.5us from SYNCPAT.

Q. When the Deserializer is disabled (REN=0), what happens to your LOCK output?
A. This will tri-state ROUT0-9, RCLK and /Lock. However, the Lock pin will only be in tri-state if the device is locked (/LOCK=0) when REN is disabled. If the Deserializer is not locked when REN is disabled, the /LOCK output will remain high and will go low if the Deserializer locks regardless of REN.

Q. Can you load the /LOCK pin with 2 loads and a cable?
A. Yes you can.

Q. Can you pull-up /LOCK output?
A. Yes, with a 2K-ohm resistor

Q. Would SYNC and LOCK signals be susceptible to noise on the cable?
A. The SYNC inputs of the Serializer are de-glitched by the pulse width requirement of those inputs. In order to be recognized as a "SYNC request" a SYNC input must be held high for at least 4 consecutive TCLK edges. Narrower pulses and glitches are ignored.

Q. What is the RCLK jitter during operation?
A. We have measured about 600 ps Peak-Peak when running at nominal conditions (40MHz/3.3V/Room Temp) sending random data.

Q. The LVDS serial output is rated for a 27ohm load. Can a different value be used?
A. Yes, you can use a different value. You should use whatever resistance matches the line that is being driven. The total RL we use is 27ohm, this would be two 54ohm resistors in parallel which represents a heavily loaded backplane. We have recommended 27ohm because our AC characteristics slightly change with higher resistance. Specifically, rise and fall times could change. Also, keep in mind that with a higher value resistor you will have a higher Vod- differential swing.

Q. Can the devices be daisy chained?
A. We do not recommend daisy chaining. The reason for this is jitter accumulation. The jitter accumulated in the serializer is passed on to the Deserializer. The jitter at the Deserializer output is amplified and it would get passed on to the next serializer. This jitter accumulation will result in lock loss.

Q. How do you terminate the bus?
A. -Point-to-point-single termination at the LVDS serial input
-Multi-drop with single termination- When your serializer is in the first slot of your bus, then you only need single termination at the far end of the bus.
-Multi-drop with double termination- When your serializer is not on the first slot of the bus, you need to use termination at each end of the bus. A 100 ohm differential bus must be terminated at each end with a 100 ohms or less depending on cap load and spacing. But it should not be any less than 54 ohms.

Q. What are some recommended interconnect media for the device?
A. We have successfully utilized the device on a backplane. We have also performed cable testing using UTP CAT 5 cable. However, a variety of media can be used as long as impedances are matched and you limit the number of transitions between media of different Zo to minimize reflections.

Q. What kind of power supply filtering is needed?
A. Bypass each device with 0.1uf/0.01uf/0.001uf in parallel. You may also want to use a bulk capacitance for each PCB. A 10uf 35V tantalum capacitor can be used.

Q. What is the major difference between DS92LV1210 and DS92LV1212?
A. The DS92LV1210 needed a SYNC pattern in order to get locked. The DS92LV1212 can lock to random data as long as the data is not a repetitive multi-transition.

Q. Describe RMT and how it effects the device.
A. RMT - repetitive multi-transition- is a specific repeated pattern. For our device, RMT occurs when there is more than one low-high transition between clock bits. The part expects to see only one permanent low-high transition and this would be CLK0-CLK1. Any time any of the bits (except Bit 9) are held low and the next adjacent bit is held high, RMT will occur. For example, B0 held low and B1 held high will create an additional low to high transition-RMT. So in an application, you need to ensure that the bits are not hard tied low/high in this manner.

Q. How close does the REFCLK frequency have to be to the TCLK frequency?
A. REFCLK frequency should fall within the following range: 0.95Tclk

Q. What are the typical lock times?
A. Typical random data lock times are 570 us at 40MHz. Typical lock time from PWRDWN is 7.4us and 14.4us from SYNCPAT.

Q. Can the DS92LV1212 replace the DS92LV1210?
A. Yes you can as long as you don't have lock time requirements that are faster than the 1212's capability. Also the 1212 has tighter frequency requirement for REFCLK relative to Tclk.

Q. Can REFCLK be removed??
A. No, as in the DS92LV1210 REFCLK runs the internal state machine.