All projects
FRITZ
Gas for DR III
Please be patient ... this area is still under construction ...
Low Noise Frontend Electronics Development
OSU_VIK1:
this picture
shows the layout of a Tiny Chip (2mm x 2mm)
which contains five prototype frontend readout circuits.
Each circuit is composed of a charge sensitive preamplifier, followed by a
shaper with peaking times between 1 and 2 microseconds, and a simple
output buffer.
This particular prototype achieved a noise performance
of 180e + 9e/pF * Cdet, where Cdet stands for the detector capacitance.
The 5pF coupling capacitors between preamps and shapers show up as
a column of dark squares towards the middle of the device,
whereas the input FETs with gate lengths between 5000 and 10000 microns
show up as rectangles towards the left.
OSU_VIK2:
another Tiny Chip project, achieving a noise performance of
120e + 7e/pF with input FET dimensions of 5000/1.8 microns.
OSU_VIK3:
our third preamp prototype circuit which includes a 5x gain stage after
the shaper in order to match the +-1V input range of the ADC's in the
SVX_CLEO backend.
The noise performance is comparable to the one achieved with the
OSU_VIK2 circuit.
The above devices
were manufactured by ORBIT Semiconductor Inc., Sunnyvale, CA,
in a 1.2 micron P-well process.
SVX_CLEO:
this picture shows the pad layout of a prototype backend chip for Si3,
which is based on the Fermilab/LBL SVXII chip. The preamp and pipeline
sections of the original SVX circuit were removed, and the 128-channel ADC
and neighbor logic were kept. Preamp support lines were added to both the
input pads (left) and output pads (right).
Si3-1:
the layout of the first 128-channel Si3 prototype frontend chip.
It includes SVXII-style shift registers with charge injection for
calibration purposes, 4 different input FET designs, 2 preamp and 2 shaper
designs, and a gain stage followed by baseline subtraction.
The output pulse height is roughly 1V for 5x minimum ionizing particles
in a silicon detector of 300 micron thickness (1 MIP = 22,500 electrons).
The projected noise performance is roughly 100e + 5e/pF.
Si3-1-Map:
a floorplan of the Si3-1 chip.
(This file is also available as a lower resolution
GIF file.)
Si3-1-Pads:
a map of the output pads of the Si3-1 chip. If multiple pad names are
present, then the upper name (in black) gives the pad name on the SVX_CLEO
chip.
(This file is also available as a lower resolution
GIF file.)
All projects
FRITZ
Gas for DR III
CLEO WEB PAGES
Updated: July 6, 1995
Author: Michael M. Zoeller (mz@mps.ohio-state.edu)
OSU_VIK1:
this picture
shows the layout of a Tiny Chip (2mm x 2mm)
which contains five prototype frontend readout circuits.
Each circuit is composed of a charge sensitive preamplifier, followed by a
shaper with peaking times between 1 and 2 microseconds, and a simple
output buffer.
This particular prototype achieved a noise performance
of 180e + 9e/pF * Cdet, where Cdet stands for the detector capacitance.
The 5pF coupling capacitors between preamps and shapers show up as
a column of dark squares towards the middle of the device,
whereas the input FETs with gate lengths between 5000 and 10000 microns
show up as rectangles towards the left.
OSU_VIK2:
another Tiny Chip project, achieving a noise performance of
120e + 7e/pF with input FET dimensions of 5000/1.8 microns.
OSU_VIK3:
our third preamp prototype circuit which includes a 5x gain stage after
the shaper in order to match the +-1V input range of the ADC's in the
SVX_CLEO backend.
The noise performance is comparable to the one achieved with the
OSU_VIK2 circuit.
The above devices
were manufactured by ORBIT Semiconductor Inc., Sunnyvale, CA,
in a 1.2 micron P-well process.
SVX_CLEO:
this picture shows the pad layout of a prototype backend chip for Si3,
which is based on the Fermilab/LBL SVXII chip. The preamp and pipeline
sections of the original SVX circuit were removed, and the 128-channel ADC
and neighbor logic were kept. Preamp support lines were added to both the
input pads (left) and output pads (right).
Si3-1:
the layout of the first 128-channel Si3 prototype frontend chip.
It includes SVXII-style shift registers with charge injection for
calibration purposes, 4 different input FET designs, 2 preamp and 2 shaper
designs, and a gain stage followed by baseline subtraction.
The output pulse height is roughly 1V for 5x minimum ionizing particles
in a silicon detector of 300 micron thickness (1 MIP = 22,500 electrons).
The projected noise performance is roughly 100e + 5e/pF.