Projects DAQ Silicon III

FRITZ: CLEO III Fastbus - VME Interface

The front-end electronics for the CsI calorimeter, the muon system, and the new CLEO III drift chamber will be implemented in Fastbus using LeCroy 1877 TDC modules. Fastbus is far less popular than VME and consequently the market for Fastbus crate controllers is small. None of the existing modules matches our requirements. In such a situation it is typically decided to start a new design hoping it will not be obsolete and out-performed by the time it is finally done. Our simpler and more satisfying solution is to make Fastbus look like VME: FRITZ -- A Fastbus Read-Out Interface with data Translation and Zero--suppression \cite{ref:FRITZ}. FRITZ consists of a standard size Fastbus printed circuit board containing not only the Fastbus interface logic and ECL drivers but also a complete VME interface including a 2 or 3-slot VME backplane. A regular VME CPU module plugged into one of the VME slots acts as Fastbus controller. A second VME slot is reserved for the CLEO III Trigger Interface Module. High performance VME CPU modules require large heat sinks and typically extend over two VME slots. To accommodate these modules Fritz will contain a 3-slot VME backplane and has an effective width of 4 regular Fastbus modules. Click here for a drawing of the VME-Fastbus interface module FRITZ. The advantages of this approach over conventional solutions include: Besides the basic Fastbus Controller functionality FRITZ contains a list driven sequencer which in combination with a VME master interface copies data from the Fastbus modules directly into the memory of the Data-Mover CPU. As an additional feature, memory look-up tables are included in the data path to perform pedestal suppression and channel tagging. Optionally, header words can be removed from the data stream.

FRITZ: General Description

The general data-flow diagram shows that FRITZ consists of several submodules interconnected via an internal 32-bit data and 18-bit address bus. The internal TTL logic is connected to the Fastbus backplane over ECL to TTL level shifters (MC10H124, MC10H125 chips) and to VMEbus via standard driver chips.
FRITZ supports two different modes of operation: a programmed I/O mode to perform single Fastbus actions for single read/write or broadcast cycles and a DMA mode for fast read-out of the whole crate.
Fastbus programmed I/O is performed by mapping each Fastbus operation to a single VME cycle: the VME slave interface and the Fastbus master interface act as master and slave of the internal bus. Through this chain the VME address/data strobes as well as the VME data words are handed over to Fastbus, and Fastbus acknowledge signals are passed back to VMEbus.
DMA operations are done in a completely different way. After being triggered by a special VMEbus cycle, a sequencer executes commands stored in a list memory. List commands include primary and secondary address cycles, data cycles, as well as block transfer operations ( Timing Diagram of Read-Out Sequence ). A cycle time of 125 ns has been acheived. This include 85 ns response time of the 1877 TDC.
Incoming data is passed on to the sparsification submodule. The sparsifier performs two threshold comparisons and replaces the 1877 channel index with a more meaningful CLEO identifier. The look-up tables are implemented using three 4k x 16-bit memories. If the data word is not rejected, it is then written into a FiFo which decouples Fastbus and VME operations. As soon as data arrive in the FiFo, the FRITZ VME master interface requests the VME bus and starts transferring the data into the Data-Mover CPU memory via VME block transfer cycles using a previously defined starting address.
The read-out DMA process comes to an end if either the last Fastbus data word has been read out i.e. the last Fastbus module returns an Fastbus SS code = 2) or an error condition is detected by the sequencer logic. In both cases the sequencer logic waits for the pipeline to empty, {\it i.e.} for the sparsifier and the VME master interface to finish their operation. Once a read-out cycle is complete, FRITZ issues an interrupt to the Data-Mover via a separate VME interrupter chip.

Picture Gallery (Postscript)

FRITZ: Mechanical Design
FRITZ: Data Flow
FRITZ: Read-Out Sequencer Timing
Projects DAQ Silicon III
CLEO WEB PAGES
Updated: Nov. 15 1995
 Author: Andreas H. Wolf (ahw@mps.ohio-state.edu)