DMB_V6 Project Status (10/10/2012 - 18:41:37)
Project File: DMB_OSU_V904_start.xise Parser Errors: No Errors
Module Name: DMB_V6 Implementation State: Programming File Generated
Target Device: xc6vlx130t-3ff1156
  • Errors:
No Errors
Product Version:ISE 12.4
  • Warnings:
860 Warnings (25 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,287 160,000 2%  
    Number used as Flip Flops 3,252      
    Number used as Latches 35      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 2,446 80,000 3%  
    Number used as logic 1,317 80,000 1%  
        Number using O6 output only 729      
        Number using O5 output only 331      
        Number using O5 and O6 257      
        Number used as ROM 0      
    Number used as Memory 852 27,840 3%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 852      
            Number using O6 output only 574      
            Number using O5 output only 5      
            Number using O5 and O6 273      
    Number used exclusively as route-thrus 277      
        Number with same-slice register load 228      
        Number with same-slice carry load 49      
        Number with other load 0      
Number of occupied Slices 1,296 20,000 6%  
Number of LUT Flip Flop pairs used 3,534      
    Number with an unused Flip Flop 825 3,534 23%  
    Number with an unused LUT 1,088 3,534 30%  
    Number of fully used LUT-FF pairs 1,621 3,534 45%  
    Number of unique control sets 373      
    Number of slice register sites lost
        to control set restrictions
1,668 160,000 1%  
Number of bonded IOBs 384 600 64%  
    Number of LOCed IOBs 380 384 98%  
    IOB Flip Flops 11      
    IOB Master Pads 38      
    IOB Slave Pads 38      
Number of RAMB36E1/FIFO36E1s 97 264 36%  
    Number using RAMB36E1 only 97      
    Number using FIFO36E1 only 0      
Number of RAMB18E1/FIFO18E1s 3 528 1%  
    Number using RAMB18E1 only 3      
    Number using FIFO18E1 only 0      
Number of BUFG/BUFGCTRLs 9 32 28%  
    Number used as BUFGs 9      
    Number used as BUFGCTRLs 0      
Number of ILOGICE1/ISERDESE1s 0 600 0%  
Number of OLOGICE1/OSERDESE1s 11 600 1%  
    Number used as OLOGICE1s 11      
    Number used as OSERDESE1s 0      
Number of BSCANs 1 4 25%  
Number of BUFHCEs 0 120 0%  
Number of BUFOs 0 30 0%  
Number of BUFIODQSs 0 60 0%  
Number of BUFRs 0 30 0%  
Number of CAPTUREs 0 1 0%  
Number of DSP48E1s 0 480 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of GTXE1s 0 20 0%  
Number of IBUFDS_GTXE1s 0 10 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 15 0%  
Number of IODELAYE1s 0 600 0%  
Number of MMCM_ADVs 1 10 10%  
Number of PCIE_2_0s 0 2 0%  
Number of STARTUPs 1 1 100%  
Number of SYSMONs 0 1 0%  
Number of TEMAC_SINGLEs 0 4 0%  
Number of RPM macros 80      
Average Fanout of Non-Clock Nets 3.46      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Oct 10 18:14:51 20120326 Warnings (0 new)141 Infos (28 new)
Translation ReportCurrentWed Oct 10 18:35:07 2012003 Infos (0 new)
Map ReportCurrentWed Oct 10 18:37:16 20120250 Warnings (13 new)10 Infos (0 new)
Place and Route ReportCurrentWed Oct 10 18:38:53 20120131 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Oct 10 18:39:22 2012002 Infos (0 new)
Bitgen ReportCurrentWed Oct 10 18:41:36 20120153 Warnings (12 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateTue Oct 2 15:36:46 2012
Physical Synthesis ReportOut of DateThu Sep 27 22:18:37 2012
WebTalk Log FileCurrentWed Oct 10 18:41:36 2012

Date Generated: 10/10/2012 - 18:41:37