DMB_V6 Project Status (10/25/2012 - 15:16:42)
Project File: DMB_OSU_V3_fifo.xise Parser Errors: No Errors
Module Name: DMB_V6 Implementation State: Mapped (Failed)
Target Device: xc6vlx130t-3ff1156
  • Errors:
 
Product Version:ISE 12.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 4,146 160,000 2%  
    Number used as Flip Flops 4,110      
    Number used as Latches 36      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 2,970 80,000 3%  
    Number used as logic 1,724 80,000 2%  
        Number using O6 output only 934      
        Number using O5 output only 369      
        Number using O5 and O6 421      
        Number used as ROM 0      
    Number used as Memory 958 27,840 3%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 958      
            Number using O6 output only 724      
            Number using O5 output only 6      
            Number using O5 and O6 228      
    Number used exclusively as route-thrus 288      
        Number with same-slice register load 233      
        Number with same-slice carry load 55      
        Number with other load 0      
Number of occupied Slices 1,791 20,000 8%  
Number of LUT Flip Flop pairs used 4,527      
    Number with an unused Flip Flop 1,001 4,527 22%  
    Number with an unused LUT 1,557 4,527 34%  
    Number of fully used LUT-FF pairs 1,969 4,527 43%  
    Number of unique control sets 583      
    Number of slice register sites lost
        to control set restrictions
3,004 160,000 1%  
Number of bonded IOBs 390 600 65%  
    Number of LOCed IOBs 386 390 98%  
    IOB Flip Flops 15      
    IOB Master Pads 38      
    IOB Slave Pads 38      
    Number of bonded IPADs 4      
Number of RAMB36E1/FIFO36E1s 116 264 43%  
    Number using RAMB36E1 only 116      
    Number using FIFO36E1 only 0      
Number of RAMB18E1/FIFO18E1s 5 528 1%  
    Number using RAMB18E1 only 4      
    Number using FIFO18E1 only 1      
Number of BUFG/BUFGCTRLs 12 32 37%  
    Number used as BUFGs 11      
    Number used as BUFGCTRLs 1      
Number of ILOGICE1/ISERDESE1s 0 600 0%  
Number of OLOGICE1/OSERDESE1s 15 600 2%  
    Number used as OLOGICE1s 15      
    Number used as OSERDESE1s 0      
Number of BSCANs 1 4 25%  
Number of BUFHCEs 0 120 0%  
Number of BUFOs 0 30 0%  
Number of BUFIODQSs 0 60 0%  
Number of BUFRs 1 30 3%  
Number of CAPTUREs 0 1 0%  
Number of DSP48E1s 0 480 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of GTXE1s 1 20 5%  
Number of IBUFDS_GTXE1s 1 10 10%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 15 0%  
Number of IODELAYE1s 0 600 0%  
Number of MMCM_ADVs 2 10 20%  
Number of PCIE_2_0s 0 2 0%  
Number of STARTUPs 1 1 100%  
Number of SYSMONs 0 1 0%  
Number of TEMAC_SINGLEs 0 4 0%  
Number of RPM macros 83      
Average Fanout of Non-Clock Nets 3.50      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Oct 23 15:41:23 2012   
Translation ReportCurrentTue Oct 23 15:42:00 2012   
Map ReportCurrentTue Oct 23 15:44:32 2012   
Place and Route ReportCurrentTue Oct 23 15:46:16 20120125 Warnings (0 new)1 Info (0 new)
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentTue Oct 23 15:46:47 2012002 Infos (0 new)
Bitgen ReportCurrentTue Oct 23 15:49:22 20120159 Warnings (12 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateTue Oct 2 15:36:46 2012
WebTalk Log FileOut of DateTue Oct 23 15:49:22 2012

Date Generated: 10/25/2012 - 15:16:42